Digital Scan Clock Gating with an External Scan Clock -- Continuous Acquisition

This LabVIEW example demonstrates the use of Digital Scan Clock Gating in conjunction with an External Scan Clock to control the acquisition of analog data. Digital Scan Clock Gating is the use of an external TTL signal (high or low) to pause a data acquisition operation. An External Scan Clock is a source, external to the device, of the TTL pulses that initiate scanning of the channel list.

You can use any PFI lines as inputs for the digital scan clock gate and External Scan Clock signals; however, the default front panel settings in the example VI are as follows:

- TTL scan clock gate input is PFI3
- TTL external scan clock input is PFI4
- If PFI3 is TTL high, and pulses are present on PFI4, acquisition can proceed

Note: PFI3 is pulled high by a pull-up resistor on the device, so if no external signal is connected, the acquisition will proceed if pulses are present on PFI4.

Requirements

Filename: 2597.vi

Software Requirements

Application Software: LabVIEW Full Development System 6.0
Language(s): LabVIEW

Hardware Requirements

Hardware Group: Multifunction DAQ (MIO)
Driver: Traditional NI-DAQ (Legacy) 6.8.0

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