Re-triggerable Pattern Output Example for 653X Devices

This VI has been designed to perform multiple triggered pattern output operations on 653X series (PCI-DIO-32HS) digital devices that have an onboard clock. Each time a trigger is received, the board will output a finite pattern, then re-arm the trigger detection hardware and wait for the next trigger. The trigger will only be re-armed after the last output operation has been completed, therefore only triggers received after the operation has been completed (and the hardware re-armed) will be detected. The time it takes to re-arm the trigger after the output operation completes is system dependent, but is optimized by using the Digital Buffer Control.VI's reserve functionality.

The Digital Buffer Control VI is used with the ¿Reserved¿ control word in order to preserve all configuration settings for the operation and the buffer allocated. By configuring the board for finite pattern generation only once and then re-using the same buffer space for each generation's buffer of output data, this VI optimizes the overhead involved in repeatedly configuring the device in software to perform finite pattern generation. Once the generation has completed, calling Buffer Control with the "reserved" control code reserves the previous buffer of memory, originally allocated with DIO Config, for the next generation. Therefore DIO Config and DIO Clear only need to be called once. By using this combination of Vis, the board can perform the triggered pattern output operation more frequently because it does not have to reconfigure itself completely for the next trigger (call the DIO Config VI).

Note that this example writes the same buffer of data out over and over. New data can be written with each iteration if it is input to DIO Write inside of the loop and its length does not exceed the number of updates originally set with DIO Config.

The pattern used by the example builds itself in order to produce a square wave on each line. As the line number increases, the period of the square wave is doubled. This way it gives the same waveform output as a counter would if we had access to all the bits (or lines) in the count register. The LSB will be assigned to the least significant line of the least significant port used.

For instructions on how to setup and use this example please refer to the Readme file and the VI documentation.

DAQ VIs USED:
DIO Config, DIG Trigger Config, DIO Write, DIO Start, DIO Wait, Buffer Control, DIO Clear.

Requirements

Filename: retrig_pat_output.zip

Software Requirements

Application Software: LabVIEW Base Development System 6.0
Language(s): LabVIEW

Hardware Requirements

Hardware Model: PCI-6534, PCI-6533
Driver: Traditional NI-DAQ (Legacy) 7.1

Reader Comments | Submit a comment »

This example in Lab Windows CVI
Is this example available for Lab Windows Cvi? I need one of this kind.
- Frank Schlachter, Robert Bosch GmbH (DE). frank.schlachter@de.bosch.com - Jul 15, 2008