NI-IMAQ I/O Internal Control Loop - Software Gated Example

This VI uses an internal timer and software gating to sample an input on a NI-IMAQ I/O FPGA device. The VI can be used to determine the rate at which an action occurs. It can also be used to choose whether or not to perform that action depending on if the value of the Run input.

This VI uses an internal timer and software gating to sample an input on a NI-IMAQ I/O FPGA device.  The VI can be used to determine the rate at which an action occurs. It can also be used to choose whether or not to perform that action depending on if the value of the Run input.

Instructions for running:

1.         Create a new LabVIEW project.

2.         Add a NI-IMAQ I/O FPGA target to the Project.

3.         Add the example VI under your FPGA target.

4.         Enter a valid Period value for the Period control.

5.         Open and run the VI from the project.

Note:

To make this VI hardware specific add this VI to your NI-IMAQ I/O FPGA target in your LabVIEW Project and replace the Run Boolean control with an FPGA I/O Node.

Requirements

Filename: imaqio_int_cloop_sw_gate.vi

Software Requirements

Application Software: LabVIEW Full Development System 8.2
Toolkits and Add-Ons: LabVIEW FPGA Module 8.2
Language(s): LabVIEW

Hardware Requirements

Hardware Group: Vision (IMAQ)
Hardware Model: PCI-8254R, NI PCIe-8255R, NI PCIe-8254R
Driver: NI-IMAQ for IEEE 1394 Cameras 2.0.2

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