8253: Generating a Continuous Pulse Train

This VI generates a continuous pulse train on the OUT pin of the chosen counter. If counter 0 is chosen, an internal timebase is used for the CLK input. If counter 1 or 2 is used, you must supply your own timebase at the CLK pin for that counter. This VI only works with Lab/1200 type devices that have an 8253/54 counter timer chip. Examples of these devices are the PCI-1200, Lab-PC-1200, and DAQCard-1200.

INSTRUCTIONS:
1. Enter the device number of your board.
2. Enter the counter number.
3. If using counter 0, enter your desired frequency. If using counter 1 or 2, enter your divisor N (the number by which you want to divide the timebase you are connecting to the CLK pin).
4. If you are using counter 1 or 2, you may optionally enter the frequency of your timebase in the "user supplied timebase (Hz)" input. This value is used to calculate the actual frequency.
5. Make the appropriate I/O connections as explained below.
6. Run the VI. The continuous pulse train will be generated on the OUTB pin for your chosen counter.

KEY PARAMETERS:
This VI shows how to use the ICTR Control.vi and Generate Pulse Train (8253).vi to produce a continuous pulse train until the STOP button is pressed.
The CLK of counter 0 is internally connected to a 1 or 2 MHz timebase (depending on your device). If you use counter 0, you do not need to connect an external timebase. However, the maximum and minimum pulse train frequencies you can output are dependent on this timebase. For example if you have a 2 MHz timebase, the highest frequency output is 2 MHz/2 = 1 MHz, and the lowest frequency output is 2 MHz/65535 = 30 Hz. This is because you must divide the timebase by a minimum of two, and can have a maximum divisor of 2^16 = 65535 for a 16-bit counter. If you need a faster pulse train you could use a different counter and supply your own faster timebase. If you need a slower pulse train you could use a different counter and supply a slower timebase, or you could use the output of counter 0 as your timebase for another counter and modify this example.
The "actual frequency" output may differ from your desired frequency because the pulse train is obtained by dividing down a timebase by a whole number. It may be that your desired frequency cannot be obtained. For example if your internal timebase is 2 MHz and you set you desired frequency to 600 kHz, you actual frequency will be 500 kHz. This is because 2 MHz/3 = 667 kHz and 2 MHz/4 = 500kHz, so 500 kHz is the closest frequency below what you chose.
Duty cycle is the ratio of the second phase (in this case the low phase) of the pulse to the period of one pulse. This example attempts to get a duty cycle of 0.50 since half of the timebase divisor is used for the high phase of the pulse and half is used for the low phase of the pulse. However, the actual duty cycle may differ. This happens when your desired frequency requires an odd number for the timebase divisor. For example if you choose a desired frequency of 95239 Hz with a 2 MHz timebase, the divisor will be 21. For this divisor, 11 pulses will be counted for the first phase and 10 pulses will be counted for the second phase. The actual duty cycle is 10/21 = 0.48.

I/O CONNECTIONS:
Using counter 0:
Connect to OUTB0 for the continuous pulse train.
Using counter 1 or 2:
Connect your external timebase to the CLK. Pin of your chosen counter
Connect to the OUT pin of your chosen counter for the continuous pulse train.
To find the actual pin numbers, refer to the hardware user manual.

DAQ VIs USED:
ICTR Control.vi, Generate Pulse Train (8253).vi.

Requirements

Filename: cont_pulse_train__8253_.zip

Software Requirements

Application Software: LabVIEW Full Development System 5.0.1
Language(s): LabVIEW

Hardware Requirements

Hardware Group: Multifunction DAQ (MIO)
Driver: Traditional NI-DAQ (Legacy)

Reader Comments | Submit a comment »