8253: Generating a Finite Pulse Train (Three Counters)

This VI uses all three counters to generate a finite pulse train on the OUT pin of counter 2. Since counter 0 is connected to an internal clock source, it is used to generate the timebase used by counters 1 and 2. Counter 1 generates a single low pulse that is passed through a 7404 inverter chip to create a high pulse to gate counter 2. Counter 2 is set up to generate a pulse train. This VI only works with Lab/1200 type devices that have an 8253/54 counter timer chip. Examples of these devices are the PCI-1200, Lab-PC-1200, and DAQCard-1200.

INSTRUCTIONS:
1. Enter the device number of your board.
2. Enter the desired frequency.
3. Enter the number of pulses.
4. Make the appropriate I/O connections as explained below.
5. Run the VI. The continuous pulse train will be generated on the OUTB pin for your chosen counter.

KEY PARAMETERS:
This VI shows how to use the ICTR Control.vi and Timebase Generator (8253).vi to produce a finite pulse train.
On the diagram, this example uses a sequence structure to divide up the main tasks. In frame 0 all of the counters are reset. In frame 1 the counters are set up for different counting modes. The first call to Timebase Generator (8253).vi sets up counter 0 in an attempt to generate a timebase at twice the desired frequency. This is because counter 2 must divide this timebase by a minimum of 2. With the second call to Timebase Generator (8253).vi, counter 2 takes this timebase and uses it to generate the desired frequency. The call to ICTR Control is used to set up counter 1 to generate a single low pulse which is used to gate counter 2. In frame 2 a delay occurs so that the finite pulse train has time to complete before the example can be run again.
The CLK of counter 0 is internally connected to a 1 or 2 MHz clock source (depending on your device). This clock source ultimately determines the frequency range of your finite pulse train. For example if you have a 2 MHz clock source, the highest timebase output from counter 0 is 2 MHz/2 = 1 MHz, and the lowest timebase output is 2 MHz/65535 = 30 Hz. Counter 2 must again divide this source by a minimum of 2, so the frequency range of the finite pulse train is from 500 kHz down to 16 Hz. This is because the timebase must be divided by a minimum of two, and can have a maximum divisor of 2^16 = 65535 for a 16-bit counter.
The "actual frequency" output may differ from your desired frequency because the pulse train is obtained by dividing down the clock source and then the timebase by a whole number. It may be that your desired frequency cannot be obtained. For example if your internal clock source is 2 MHz and you set you desired frequency to 41 kHz, your actual frequency will be 40 kHz. This is because counter 0 tries to create a timebase of 82 kHz, but the actual turns out to be 80 kHz. When this is used as the timebase by counter 2, the result is a 40 kHz output.
Duty cycle is the ratio of the second phase (in this case the low phase) of the pulse to the period of one pulse. This example attempts to get a duty cycle of 0.50 since half of the timebase divisor is used for the high phase of the pulse and half is used for the low phase of the pulse. However, the actual duty cycle may differ. This happens when your desired frequency requires an odd number for the timebase divisor.

I/O CONNECTIONS:
Connect OUT0 to CLK1 and CLK2.
Connect OUT1 to GAT2 via a 7404 inverter chip.
To find the actual pin numbers, refer to the hardware user manual.

DAQ VIs USED:
ICTR Control.vi, Generate Pulse Train (8253).vi.

Requirements

Filename: finite_pulse_train__8253_.zip

Software Requirements

Application Software: LabVIEW Full Development System 5.0.1
Language(s): LabVIEW

Hardware Requirements

Hardware Group: Multifunction DAQ (MIO)
Driver: Traditional NI-DAQ (Legacy)

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