Output Short Circuit Testing Technical Details (IOSH, IOSL)
This document will discuss the technical details of testing the output short circuit current of digital semiconductor devices using a test system created with the PXI platform. To learn more about the software components of this test system, click here. To return to the DC Parametric Testing Reference Architecture main page, click here.
Output short circuit current tests simulate worst-case loading conditions on the output pin of a digital device. These tests can be conducted on a wide range of devices from digital semiconductor chips to fully integrated consumer electronics devices. This paper will describe, in detail, the process of testing the output short circuit current capability of a packaged semiconductor chip using a PXI-4130 Source Measure Unit being used as the load as well as the measurement device.
Section 1: Hardware Setup
Performing output short circuit current tests using this PXI system are require two main connections – there must be a connection from the Utility Channel (channel 0) of the PXI-4130 Power SMU to the VDD and VSS terminals of the chip in order to provide power, and there must be a connection from the pin under test to the SMU channel of the PXI-4130 which acts as a constant voltage source at the opposite logic state of the pin’s output value, and then measures the resulting current flow.
Figure 2: Test Setup for Output Short Circuit Current
To perform an output short circuit test (IOS) in the logic-high state, the device pin must first be preconditioned to be a logic-high, then the SMU must be set to apply a voltage of 0V, simulating a short circuit from the pin to ground. This will result in a large amount of current flow from the output pin, stressing the output circuitry.
In order to make sure that the device doesn’t damage itself, there are two strategies that can be used:
1) Only allow the short circuit to last for a certain amount of time (usually a few milliseconds) as to prevent damage from overheating, or
2) Limit the output current that the SMU draws to a value below what will overheat the device to the point of failure.
One or both of these methods can be used during testing. In this example, the current is limited (for example 20mA) to ensure that the device does not overheat regardless of the time duration of the short circuit. To yield a pass/fail result, the current output from each pin is measured by the SMU. Under short circuit conditions, each of the pins should hit the current limit of 20mA if they are working properly. Defective pins, on the other hand, would not be able to provide this much current, therefore a pass/fail threshold of 18mA can be used to gauge the health of each pin’s output circuitry.
Testing for IOS in the logic-low state is very similar, except that the output pin is set to 0V (or VSS) and the SMU is set to 3.3V simulating a short circuit between the output pin and VDD. In this case, the SMU is the source and the chip must dissipate the current. Again, current limiting or time limiting can be employed to protect the device. In this example, a threshold of 18mA can again be used to gauge the health of these pins – in this case, by making sure they can dissipate a certain amount of current without a problem.
Automated Test Steps
Step 1: Power the DUT by applying VDD
To power the DUT, the PXI-4130 SMU should be set to output the rated voltage of the device (usually 3.3V). In addition to this voltage setpoint, it also very important to set a current limit to ensure that the DUT does not draw excessive currents if it is faulty or shorted.
Step 2: Condition the DUT outputs to logic-high states
The next step is to make sure that any bidirectional pins are set to be outputs. For an IOS high test, all outputs must be set to the logic-high state, for an IOS low test, all outputs must be set to the logic-low state. Interfacing with and conditioning a DUT can be done through a variety of different hardware configurations. In this case, a PXI-6552 100MHz High Speed Digital I/O device is recommended because it provides a high level of flexibility in terms of voltage levels and clocking, and because it can be used for digital characterization during other tests.
Step 3: Switch to the channel to be tested
For automated setups, a switching system must be utilized to gain the most speed and repeatability. Like the other tests shown in this reference architecture, the same PXI-2535 high-density matrix switch can be employed to allow the PXI-4130 SMU communicate to all the pins under test. At this point, since all pins have been conditioned to the logic-high state and the SMU is already configured, the matrix simply needs to connect the SMU to the pin under test and measurements are ready to be made.
Step 4: Measure the current
Once the SMU is configured, the device is conditioned, and the pin-under test is connected, measuring the current using the SMU will yield a measure of the health of a pin. For an IOS high test, the current will flow into the SMU and should be at least an expected negative amount (in this example the threshold is -18mA, where the hardware limit is set to 20mA). For an IOS low test, the current will flow out of the and the current should be at least a certain positive amount (in this example the threshold is 18mA, where the hardware limit is set to 20mA).
If the pin can source or sink enough current, then it is deemed to be passing.
Step 5: Switch to the next channel and repeat.
Repeat steps 3 and 4 for each output pin on the device under test, combining all results into an array for easy display and analysis.
Section 2: Software Setup
The software for this Output Short Circuit Test is developed using NI LabVIEW and NI Switch Executive. LabVIEW is used as the primary Application Development Environment (ADE) while Switch Executive is used to configure routes on the high-density matrix. For simplicity, only the Output Short Circuit High (IOSH) test is incorporated into the code. To include the IOSL test, add steps to the code as per the description above.
The following software versions were used to implement the Opens and Shorts Semiconductor Test:
LabVIEW 8.5 Graphical Programming Environment
Switch Executive 2.1.1 Switch Management Software
The LabVIEW code described in this document can be downloaded from the link at the top of this document.
Note: Functional blocks in the LabVIEW graphical programming language are known as ‘Virtual Instruments’ or ‘VIs’. The acronym ‘VI’ will therefore be used when describing procedures in this section.
The software steps to test the current draw are as follows:
Step 1: Initialize the SMU based on the resource name and set the voltage level and current limit autorange features on the device to 'On'. Next, Set the utility channel on the SMU to power your device by changing the voltage setpoint. Set the current limit to the max allowable current in order to protect your device and test setup.
Step 2: If necessary, add digital I/O code here to condition your DUT to the appropriate logic state such that all pins to be tested are configured as outputs in the logic-high state.
Step 3: Next, set the SMU channel on the PXI-4130 to 0V. This SMU channel will be switched to each pin in the output-high state effectively shorting each output pin under test.
Step 4: Initialize a session to the matrix switch via NI Switch Executive. The NI Switch Executive (NISE) Virtual Device Name is input to the Open Session VI to begin communication with all the switches in the system. The individual routes to each pin on the device under test are retrieved from the route group specified, and used later to make the connections. To download the "extract_routes" subVI and an example NI Switch Executive configuration, return to the software components section of this reference architecture.
Step 5: For each pin on the device under test (as specified by each route in the route group), make a connection to the pin and then perform a current measurement on the SMU channel of the PXI-4130 to measure the current flow through the CMOS transistors on each pin. Once this measurement has been taken, disconnect from the pin and repeat the process on the next.
Step 5: Show a histogram of the pin measurements and display the individual values in a table.
Step 6: Power down and close SMU session.
Step 7: Disconnect all switch channels and close switch session.
The front panel of the attached example code allows the user to control the settings of the SMU, Switch and HSDIO instrument. It displays results of the IOS test using a text array as well a histogram.
- Reference Architecture: DC Parametric Semiconductor Validation Test
- NI PXI-4130 Power SMU
- NI PXI-2535 FET Switch
- Switch Executive demonstration video
Application Software: LabVIEW Professional Development System 8.5, NI Switch Executive 2.1
Hardware Group: High-Speed Digital I/O, Power Supplies, Switches
Hardware Model: PXI-2535, NI PXI-4130, PXI-6552
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