Input Leakage Testing Technical Details (IIL, IIH)
This document will discuss the technical details of testing the input leakage current on semiconductor devices using a test system created with the PXI platform. To learn more about the hardware components of this system, click here. To learn more about the software components of this system, click here. To return to the DC Parametric Validation Test Reference Architecture main page, click here.
Leakage tests can be conducted on a wide range of devices from discrete components to semiconductor chips to fully integrated consumer electronics devices. This paper will describe, in detail, the process of testing the input current leakage on a packaged semiconductor chip. Input leakage tests are performed by measuring the amount of current flow into a high-impedance input pin on a chip.
Ideally, the input pin would have an infinite impedance and no current would flow into or out of it, but in actuality it will have a very large (but finite) impedance resulting in a very small current flow to and from the device. This effect is illustrated below - shown at the left is the input circuitry of a standard digital input pin on a CMOS device including protection diodes and input transistors. On the right is the effective resistances to VDD and VSS seen at the pin. For properly functioning devices these leakage resistances should be as high as possible, therefore the currents that flow through them should be very small, generally uA-level and below.
Figure 1. Actual input circuitry for a standard CMOS digital pin (left) and equivalent leakage resistances (right)
In order to measure and characterize this small current flow, a source measure unit (SMU) is used to provide the voltage source as well as measure the resulting current. Since most leakage currents are at the uA level and below, using the most sensitive range available on the SMU is important for achieving the best results.
Section 1: Hardware Setup
Since leakage tests are powered tests, there must be power provided to the chip through its VDD and VSS terminals. Simultaneously, an SMU channel is needed to provide the voltage and measure the current to each digital I/O pin. Since the PXI-4130 SMU offers a power supply channel as well as an SMU channel on the same PXI module, leakage testing can be done using a single measurement module. Additionally, a PXI-2535 high density switch can be used to provide the SMU with connectivity to up to 136 digital pins. Shown below are the connections for using the PXI-4130 to power a chip with its utility channel and perform a leakage test with its SMU channel. Switching can be added between the SMU channel and the DUT as necessary.
Figure 2: Leakage Test Connections (Switching Not Shown)
For an input leakage high (IIH) test, a logic-high voltage level (usually 3.3V) is applied to an input pin using the PXI-4130 SMU. Ideally, the input pin would have an infinite impedance and no current would flow, but in actuality it will have a very large (but finite) impedance resulting in a very small current flow into the device, through its VSS terminal and back to the negative terminal of the SMU. In this case the PXI-4130 SMU is sourcing the leakage current. Since most leakage currents are at the uA level and below, using the most sensitive range available on the SMU is important for achieving the best results - in this case the PXI-4130 SMU can be set to its 200uA range which provides 1nA current measurement resolution.
Figure 3. Input Leakage High (IIH) Test
For an input leakage low (IIL) test, a logic-low voltage (usually 0V) is applied to the input pin and the resulting current is again measured. However, in this case, the current flows from the VDD of the chip, through the internal leakage resistance, out of the pin and into the SMU - in this case, the SMU is required to sink current. This is one of the many circumstances during DC parametric testing that the 4-quadrant output available on the PXI-4130 SMU is essential for the test being performed.
Figure 4. Input Leakage Low (IIL) Test
Automated Test Steps
Step 1: Power the DUT by applying VDD using the utility channel of the PXI-4130
To power the DUT, the utility channel on the PXI-4130 SMU should be set to output the rated voltage of the device (usually 3.3V). In addition to this voltage setpoint, it also very important to set a current limit to ensure that the DUT does not draw excessive currents if it is faulty or shorted.
Step 2: Switch the SMU to the signal pin to be tested
An external switching system front end can be utilized to automate input leakage testing. The switching system can scan through pre-configured states, creating the required current and ground paths to the signal pins of the semiconductor device. There, the source measure unit can force the required voltages and measure the resulting leakage currents from each signal pin to ground.
Step 3: Set the SMU channel of the PXI-4130 to force a logic-high voltage
In most cases, a logic-high will be 3.3V. When setting the voltage level of the SMU, it is also important to set a current limit to make sure the pin doesn't draw excessive currents as a result of an internal short. In most cases, however, this test is performed after an opens/shorts test, minimizing the occurrence of this risk.
Step 4: Measure the Current to test for IIH
Measuring the current when a logic-high is applied to an input pin will yield the IIH of that particular pin. This value can then be compared to the acceptable limits of the leakage current for that device which are usually in the uA range or below. Any leakages below this limit indicate proper input structure of the DUT whereas leakages above this limit indicate structural faults on that pin's input circuitry.
Step 5: Set the SMU channel of the PXI-4130 to force a logic-low voltage
In most cases, a logic-low will be 0V. When setting the voltage level of the SMU, it is also important to set a current limit to make sure the pin doesn't source excessive currents as a result of an internal short to VDD. In most cases, however, this test is performed after an opens/shorts test, minimizing the occurrence of this risk. Since the voltage on the internal electronics of the pin will be somewhere above 0V, the SMU will sink current.
Step 6: Measure the Current to test for IIL
Measuring the current when a logic-low is applied to an input pin will yield the IIL of that particular pin. This value can then be compared to the acceptable limits of the leakage current for that device which are usually in the uA range or below. Any leakages below this limit indicate proper input structure of the DUT whereas leakages above this limit indicate structural faults on that pin's input circuitry.
Repeat steps 2 through 6 until all pins have been tested
Section 2: Software Setup
For simplicity, the software example shown below only tests for Input Leakage Low (IIL). The software for this test was developed using NI LabVIEW and NI Switch Executive. LabVIEW is used as the primary Application Development Environment (ADE) while Switch Executive is used to configure routes on the high-density matrix.
The following software versions were used to implement the Input Leakage Test:
LabVIEW 8.5 Graphical Programming Environment
Switch Executive 2.1.1 Switch Management Software
The LabVIEW code described in this document can be downloaded from the link at the top of this document.
Note: Functional blocks in the LabVIEW graphical programming language are known as ‘Virtual Instruments’ or ‘VIs’. The acronym ‘VI’ will therefore be used when describing procedures in this section.
The software steps to test for input leakage are as follows:
Step 1: Initialize the SMU based on the resource name and set the voltage level and current limit autorange features on the device to 'On'. Next, Set the utility channel on the SMU to power your device by changing the voltage setpoint. Set the current limit to the max allowable current in order to protect your device and test setup.
Step 2: If necessary, add digital I/O code to condition your DUT to the appropriate logic state such that all pins to be tested are configured as inputs.
Step 3: Next, set the SMU channel on the PXI-4130 to be at 0V in order to draw leakage current from the input pin under test. This setup is used to implement the Input Leakage Low (IIL) test.
Step 4: Initialize a session to the matrix switch via NI Switch Executive. The NI Switch Executive (NISE) Virtual Device Name is input to the Open Session VI to begin communication with all the switches in the system. The individual routes to each pin on the device under test are retrieved from the route group specified, and used later to make the connections. To download the "extract_routes" subVI and an example NI Switch Executive configuration, return to the software components section of this reference architecture.
Step 5: For each pin on the device under test (as specified by each route in the route group), make a connection to the pin and then perform a current measurement on the SMU channel of the PXI-4130 to measure the input leakage value. Once this measurement has been taken, disconnect from the pin and repeat the process on the next.
Step 5: Show a histogram of the pin measurements and display the individual values in table.
Step 6: Power down and close SMU session.
Step 7: Disconnect all switch channels and close switch session.
The front panel of the attached example code allows the user to control the settings of the SMU, Switch and HSDIO instrument. It displays results of the IIL test using a text array as well a histogram.
To add an input leakage high test into the same framework, add steps to set the SMU to a logic-high state and then measure on each pin.
- Reference Architecture: DC Parametric Semiconductor Validation Test
- NI PXI-4130 Power SMU
- NI PXI-2535 FET Switch
Application Software: LabVIEW Professional Development System 8.5, NI Switch Executive 2.1
Hardware Group: High-Speed Digital I/O, Power Supplies, Switches
Hardware Model: PXI-2535, NI PXI-4130, PXI-6552
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