DSA Module Synchronization Reference Design for Multiple cRIO Chassis

This reference example demonstrates how to synchronize multiple cRIO chassis with dynamic signal acquisition (DSA) modules in them.
A digital I/O module is used to create a reference clock which is shared amongst all of the chassis. Each chassis receives the reference clock and uses a resampling algorithm in the FPGA to send the synchronized data to the RT controller.
The example uses FPGA code which supports up to 28 channels of analog input, but requires at least a 3M gate backplane such as the NI 9103 or NI 9104.

Hardware Setup

Dynamic signal acquisition modules are more difficult to synchronize due to the fact that they are based on delta-sigma ADCs.  Unlike a SAR ADC which can be clocked directly, delta-sigma ADCs require a constant oversample clock which at some multiple of the actual sample rate.  One challenge is that due to the high frequency nature of these clocks and signal integrity concerns, it is not possible to share these clocks between cRIO chassis.  To work around this problem, a NI 9401 digital I/O module is used to generate a reference clock for all of the cRIO chassis in the system.  A resampling algorithm in FPGA is used to generate a fixed number of samples between each rising edge of the reference clock.  Since every system uses the same reference clock, the data is all synchronized.

Below is an example configuration based on the NI 9234:

The example is written to work for the NI 9239, but can be modified to work with any delta-sigma based module such as the NI 9234, NI 9225, NI 9237, etc.

Example Code

The example code on RT demonstrates how to scale the synchronized data and then either log one channel locally to disk using the TDMS file format or to stream one channel to a host PC over TCP/IP.  The TCP/IP code leverages the STM 2.0 or later component which can be download at:

STM Reference Library

Synchronization Results

The resampling technique can synchronize the measurement channels to an accuracy of better than 150ns.  Here are some results:

These results are from synchronized NI 9234s acquiring a 1 kHz sine wave at 51.2kS/s.  Over 1000 iterations produced an average mismatch of 14 ns and standard deviation of 50 ns.  The cable connecting the systems was roughly 6 inches long.

One nice aspect of this synchronization technique is that the reference clock which is shared between chassis is relatively slow.  At 50kS/s, the reference clock has a frequency of 1 kHz.  The NI 9401 is capable of driving this reference clock over long distances.  Below is a histogram of synchronization results with the some configuration as above, but with a 100 ft cable of RG-62 between the master and slave chassis.

Here you can see a similar distribution as in the short cable case, but that the mean is located near 115ns.  This shift of the histogram is due to the cable delay.  The nominal delay of RG-62 cable is 1.2ns/ft, so we would expect a total delay of roughly 120ns which matches our synchronization results.

 

Requirements

Filename: crio_sync_dsa.zip

Software Requirements

Application Software: LabVIEW Base Development System 8.6
Language(s): LabVIEW

Reader Comments | Submit a comment »