Reference Applications for cRIO Order Analysis Using a High Speed Tach

Introduction

When performing order analysis on cRIO, it is common to acquire the vibration signals and the tachometer signals with different modules and at different rates.  This document contains two example programs which demonstrate how to synchronize the vibration and tachometer measurements and how to compensate for the pipeline delays inherent to Delta Sigma based NI C-Series modules (like the NI 9234). 

• The first example program [RT] Cont Acq (Digital Tach).vi acquires the tachometer signal with an NI 9403.  This TTL high-speed digital module has 32 input channels and may be sampled at over 140 kHz.  The example may actually be reduced in complexity if used with faster digital modules like the NI 9401.
• The other example program [RT] Cont Acq (Analog Tach).vi acquires the tachometer signal with an NI 9221.  This 12 bit high-speed analog input module has an extended input range of +/- 60V and may be sampled at over 700 kS/s.
• Both example programs acquire the vibration data with an NI 9234.  This 24 bit module uses ADCs that are based on a Delta Sigma architecture and whose internal pipelines introduce a constant delay to the acquired data.  If phase information is of interest then you must compensate for this delay. See the section titled "Phase Compensation" for more information.

Both example programs are built using the cRIO Waveform Acquisition VIs.  The waveform VIs are included with this download but if you wish to learn more please see the developer zone document Reference Applications for cRIO Waveform Acquisition.

Figure 1: cRIO Waveform VIs Acquiring Vibration and Tachometer Signals

 

 

Project Overview

cRIO OAT HS Tach.lvproj includes two examples each with their own FPGA and RT VI.  One example acquires the tachometer signal with an analog module (NI 9221) and one acquires the tachometer signal with a digital module (NI 9403).

Figure 2. Project Overview

1. The [Shared] RT RIO Acq directory includes all the cRIO Wfm VIs used to configure and perform data acquisition on the RT target.
2. The two VIs labled Examples are the top level RT applications responsible for collecting and processing the vibration and tachometer data. 
3. The FPGA section has two main VIs.  The Digital Tach and Analog Tach FPGA VIs are referenced to their corresponding version of [RT] Cont Acq... VI.  These FPGA VIs are responsible for acquiring and synchronizing both the vibration and tachometer measurements.

 

FPGA VI Concept

The NI 9234 is a Delta Sigma based architecture which uses an internal 13.1072 MHz timebase to derive its sample clock.  The 9221 and the 9403 (or any other analog SAR or digital input module) perform their acquisition based off of the 40 MHz top level FPGA clock. These two clocks run asynchronously to each other and cannot be shared.

Figure 3: Delta Sigma and Non Delta Sigma modules cannot share or synchronize their timebases

This reference design implements a buffered event counting technique so that both the vibration and tachometer measurements are based off of the same time domain.  The event is a tach edge that is detected by either an analog or digital module and the time of that event is represented by counting the number of 9234 timebase ticks.  As a result the relationship between the vibration and the tachometer data is immune to timebase drift.

Figure 4: FPGA VI implements a buffered event counting technique to represent tachometer data

 

Architecture of FPGA VIs

When you open either one of the FPGA VIs you will immediately notice three parallel loops.  

Figure 5: General Architecture FPGA VIs

1. Top Loop - The top loop monitors the tachometer signal with either a digital or analog module.    
2. Middle Loop - The middle loop counts the NI 9234 timebase ticks and latches its value to the DMA FIFO when a tach edge is detected by the top loop.
3. Bottom Loop - The bottom loop performs the analog acquisition on the vibration data with the NI 9234.  Though not shown in Figure 5.  The bottom loop also arms the counter in the middle loop when the first data point is acquired.

 

Architecture of Top Level RT VIs

[RT] Cont Acq (Digital Tach).vi and [RT] Cont Acq (AnalogTach).vi are very similar.  The only difference is the analog tach version has settings for analog threshold and hysteresis.  

Figure 6: General Architecture of Top Level RT VIs

The data acquisition tasks are performed by the cRIO Waveform Acquisition VIs.  After the data is acquired, the vibration and tachometer measurements are fed to a series of Order Analysis VIs.  The NI Order Analysis libraries are part of the Sound and Vibration Measurement Suite. 

The first two order analysis VIs receive the buffered tachometer events and build a tachometer speed profile.  The subsequent VIs resample the vibration data from even-time (dt) to even-angle (dr) and perform both magnitude and phase calculations.

 

Phase Compensation

Be aware that some C Series modules (like the NI 9234) have analog to digital converters that are based off of Delta Sigma technology.  Delta Sigma ADCs introduce a significant but deterministic delay to the acquired data.  If phase information is a concern then this constant-time delay must be corrected.  

Compensating for the delay is straightforward.  You simply must add the constant-time delay to each timestamp generated by the buffered event counter.  For best results it is recommended to measure the delay introduced by your hardware combination.  To begin feed a zero phase reference signal to your cRIO system. 

Figure 7: Zero Phase Reference Signal

The reference application will calculate the phase offset that was introduced and then express that delay in terms of samples.  This constant-time delay is independent of input frequency but will change with the 9234 sample rate.  The simplest case involves an input signal less than 100Hz and you should expect a delay of approximately 40.1 samples.  The delay will vary slightly based on which NI C-Series module is acquiring the tachometer signal.

Figure 8: 1st order phase results before and after delay compensation

 

Prerequisite Hardware

The LabVIEW project requires a cRIO controller, an FPGA embedded chassis, and NI C Series modules.  The digital tachometer example requires an NI 9234 for vibration measurements and a digital module for tachometer measurements.  The analog tachometer example requires an NI 9234 for vibration measurements and a SAR based analog input module for tachometer measurements.

The project is currently configured for an NI 9403 (digital) or an NI 9221 (analog).

 

Prerequisite Software

The LabVIEW project requires the following National Instruments software:

• LabVIEW 8.6 or later
• LabVIEW Real-Time 8.6 or later
• LabVIEW FPGA 8.6 or later
• NI-RIO 3.1 or later
• Sound and Vibration Measurement Suite 2009 or later

Related Links

Developer Zone: Reference Applications for cRIO Waveform Acquisition - The cRIO Waveform VIs are included in this download, but you can find the documentation and a separate download from this location.

Product Page: NI Sound and Vibration Measurement Suite

 

Discussion and Feedback

This reference application was created by the NI Systems Engineering group.

We do not regularly monitor Reader Comments posted on this page.  Please submit your feedback to the cRIO Waveform Reference Applications discussion forum.

Requirements

Filename: tach_crio_refdesign_v10.zip

Software Requirements

Application Software: LabVIEW Full Development System 8.6
Toolkits and Add-Ons: LabVIEW Real-Time Module 8.6, LabVIEW FPGA Module 8.6
Language(s): LabVIEW

Hardware Requirements

Driver: NI-RIO 3.1

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