FPGA Servoing for Power Amplifier Test on the NI PXIe-5644R
This paper explains and provides a download of an example application for the NI PXIe-5644R vector signal transceiver (VST), which uses the VST to level the output of an RF power amplifier. The IP is capable of continuously measuring and adjusting the output power of the PA, which differs from traditional techniques that make these measurements and adjustments in series. The parallel leveling in this example results in much faster performance than traditional methods. This paper also explains some of the top-level FPGA IP, which is used in the VST FPGA code. The example application is based on the VST Simple VSA/VSG (NI 5644R, 5645R) sample project.
Table of Contents
- Traditional PA Leveling Method
- Hardware-Based Leveling Method
- Determining When the DUT Is Leveled
- Thermal Droop Compensation
- FPGA IP Details
In wireless communication systems, a power amplifier (PA) IC increases the signal strength before sending it to the antenna. PAs are typically specified to a certain performance at a particular output power level. Consequently, it is important to test them while operating at that output power level. However, the PA gain is typically only roughly known (for example +/- 3 dB) and is non-linear over the operating range of the device. The closer you get to the maximum output power, the lower the gain. For these reasons, you must "level" the PA output prior to taking any performance measurements. Leveling the output is often called power leveling or power servoing. The basic principle is to adjust the power of the signal going into the PA until the correct power level is measured coming out of the PA.
Traditional PA Leveling Method
The traditional test setup for measuring a PA is shown in Figure 1. A vector signal generator (VSG) generates a stimulus waveform to the PA device under test (DUT). A power meter ensures the DUT outputs the correct power level, and then a vector signal analyzer (VSA) measures the performance of the DUT (such as an EVM or ACP). These measurements are taken for a variety of center frequencies and power levels.
Figure 1. Traditional PA Test Setup
For each desired center frequency and power level the PA output power must be leveled. The leveling process may follow these steps:
- Pick a starting VSG power level, based on the estimated gain of the DUT.
- Set the VSG power level.
- Wait for the VSG to settle.
- Wait for the DUT to settle.
- Take a measurement with the power meter.
- If power is in range, exit. If it is not, compute the new VSG power level and return to step 2.
Leveling can take a few hundred milliseconds or several seconds, depending upon the type of DUT, the accuracy required, and the instrumentation used. After the leveling, performance measurements are taken using the VSA.
Figure 2 shows the output of an example DUT during leveling to an average output power of 28 dBm using the traditional method. If the PA gain were linear and matched the typical gain specified in the data sheet, the first point generated by the VSG would have produced an output power of 28 dBm. Instead, the PA output is only 26.5 dBm, which demonstrates the inaccuracy of the typical gain specification of the PA. Consequently, the VSG output power is adjusted and another point is captured by the VSA. This time the average power is 27.6 dBm, which demonstrates the compression of the PA gain response. In total, it took seven steps and over approximately 150 ms for the output of the PA to reach the desired level. In this example, the DUT settling time was 10 ms per step. However, settling time can vary from one DUT to the next, which greatly affects the overall leveling time.
Figure 2. Graph of Traditional Leveling
Hardware-Based Leveling Method
The NI PXIe-5644R vector signal transceiver (VST) combines the features of a VSA, a VSG, and a user-programmable FPGA. The combination allows you to move the power-leveling algorithm into hardware. Notice that even though there is no power meter shown in Figure 3, you would typically run a system calibration step to transfer the accuracy of a power meter to the VSA.
Figure 3. Vector Signal Transceiver PA Test Setup
The steps associated with leveling the PA output power are similar to the steps of the traditional method except that the leveling loop can be run inside the FPGA on the VST. Running the loop inside the FPGA greatly reduces the time required to make each adjustment. Figure 4 shows that the Auto Level IP has been added to the FPGA. The IP operates in parallel with the rest of the VSA and VSG code because it doesn't interfere with the VSA and VSG functionality of the instrument. The IP can measure the average power received by the VSA and can adjust the power being sent out the VSG.
Figure 4. VST with Auto Level IP added
You can use hardware-based leveling in a way that is similar to the traditional method. In this case, the main improvements are that the data no longer must be transferred to or from the host computer and that you can calculate the new VSG output power in real time inside the FPGA. However, by taking advantage of control theory, you can achieve even greater speed by leveling the PA output power while the DUT settles.
Figure 5 shows the control loop for the traditional leveling process. You execute each step serially, waiting for the previous step to fully settle before continuing. This ensures that the loop completes in the fewest possible number of steps, although each step takes a long time.
Figure 5. Traditional Leveling Loop
Alternatively, you can repeatedly update the loop while the DUT settles. You execute each step in parallel. You must perform more steps, but you ensure that the loop completes in the smallest possible amount of time. The power measurements will have some error associated with them because the DUT is still settling while you make each power measurement. However, this approach works correctly because the error decreases to zero as the DUT output power converges on being leveled.
Figure 6. Leveling Loop with Parallel Settling
You can make two more improvements to this model using the FPGA on the VST. Firstly, you can set the VSG output power. Traditionally, the front end of a VSG contains amplifier stages, attenuator stages, and switches to select the output power. Stages and switches take time to set and settle. You can avoid delay by inserting a Digital Gain control into the digital I/Q data path of the VSG and linearly controlling the VSG output power using the digital gain. You set the actual VSG output power only once, and the rest of the loop iterations are controlled using the digital gain. Setting the output power provides immediate settling of the VSG output power and a linear response.
Secondly, you can improve the length of averaging you use to measure the power. For example, for a particular LTE waveform, you may need to average about 1 ms of acquired data to get an average power measurement with the VSA that is repeatable to within 0.01 dB. The obvious choice is to average that amount on every loop iteration. However, for the first several loop iterations, the gain estimate is considerably off from the DUT actual gain. Instead, you can employ an averaging schedule in which the first few loop iterations use shorter averages (executing faster but getting a less accurate reading of the average power), and then as the loop starts to converge, you use longer averages to get a very accurate reading of the average power. Using an averaging schedule allows the loop to quickly get close to leveling and then slow down to complete the leveling process. Figure 7 shows an example of a leveling loop. The "settle VSG" step is replaced by a simple digital gain adjustment (DG). The "measure power" step increases in length as the loop progresses. The DUT settles at the same time in parallel.
Figure 7. Leveling Loop with Averaging Schedule
Employing this technique, you can level the DUT output power in considerably less time. For the DUT in this example, leveling takes only about 5 ms, compared to 150 ms with the traditional method. Notice that the hardware-based method took one step more than the traditional method; however, the overall time required to level was drastically less. Figure 8 shows that the first several steps occur very quickly (shorter average time), and then the points are spaced further apart as the loop converges on being leveled.
Figure 8. Graph of Hardware-based Leveling
Determining When the DUT Is Leveled
You must determine when the DUT is at the desired output power level. You would typically consider the DUT output power to be leveled when the output power is within the desired range (for example +/-0.05 dB). However, the output power no longer changes quickly. Figure 9 shows that although the first measured point is within the desired range (red dashed lines), the second point is not. Fortunately, the algorithm did not stop when it measured the first point within the desired range.
The following "in range" criteria are used in this Auto Level IP:
- The averaging schedule reached the minimum number of steps by using the final averaging time.
- The measured output power is within the specified limits.
- The VSG output power changed very little between the last step and this step.
Figure 9. Limits for determining if the DUT is leveled
Thermal Droop Compensation
With some PAs, the gain continues to decrease after the initial leveling is complete. This phenomenon is known as thermal droop, or a thermal tail. Figure 10 shows the thermal droop on the DUT used in this example with the traditional leveling method. The DUT output levels, and then the VSG output level holds constant while the VSA continues to take measurements for another 10 seconds. You can see that the output leveled to 28 dBm in about 150 ms, and then as the VSG output level held constant, the PA output power drooped by 0.1 dB over the next 10 seconds. The entire thermal tail for our example DUT is in fact much longer than 10 seconds, and it continues to droop slowly for several minutes.
Figure 10. Thermal Droop with Traditional Leveling
After you initially level the DUT output power, you need to take performance measurements using the VSA. However, the performance measurements are affected because the DUT output power continues to droop. The traditional solution has been to slow down the leveling process to account for the "steep slope" part of the droop, which occurs in the first 2 seconds for the DUT used in this example. Slowing down does help, but it doesn't fully account for the droop, and doing so takes 2 seconds.
Rerunning this same experiment using the hardware-based leveling method, you can see a little bit more droop because the leveling completes much faster. Consequently, you compensate for less of the "steep slope" part of the droop.
Figure 11. Thermal Droop with Hardware-based Leveling
You can artificially slow down the hardware-based leveling method by setting a minimum number of iterations required before leveling is considered complete. Setting a minimum allows you either to continue leveling during the "steep slope" part of the droop for DUTs with significant droop or to level quickly for DUTs with little droop. This method is an improvement over the traditional method. However, there is an even better method.
Because the hardware-based method uses a VSA to take both the performance measurements and the power level measurements, and because the Auto Level IP runs in parallel to the rest of the VSA and VSG data paths, you can continue to make minor adjustments to the VSG output level after completing the initial leveling while the performance measurements are being taken.
Figure 12. Continuous Leveling
When you enable continuous hardware-based leveling, you get the results shown in Figure 13. In this case, the initial leveling occurs in about 5 ms, and the VSG output is held roughly constant for the next 10 seconds. You allow the VSG output to update in approximately 0.001 dB steps to compensate for the droop in the DUT output. The DUT output power level holds constant. Because the continuous leveling occurs in parallel to the normal VSA data path, you can use the VSA at the same time to take performance measurements.
Figure 13. Continuous Hardware-based Leveling
FPGA IP Details
The NI 5644R VST software includes a Simple VSA/VSG (5644R, 5645R) sample project. Figure 14 shows a portion of that sample project, which has been modified to include the Auto Level IP. The Auto Level IP consists of a single FPGA VI (highlighted in red) placed in parallel with the VSA I/Q data path (highlighted in blue). The I/Q data splits and sets to both the Multirecord Acquisition VI and the Auto Level VI. This process leaves the VSA I/Q data path unchanged and allows the Auto Level VI to "snoop" on the data. The Auto Level VI returns a new digital gain value that uses a local variable to send to a new Digital Gain VI, which has been inserted in the VSG data path.
Figure 14. VSA Data Path and Auto Level IP
Figure 15 shows a new Digital Gain VI added in the VSG I/Q data path. If you set that digital gain value to 1, no change will be made to the normal VSG output. However, that digital gain can be reduced to linearly control the VSG's output level. The Auto Level IP uses this.
Figure 15. VSG Data Path and new Digital Gain VI
Documentation for the subVIs contained within the FPGA code for this example is included with the example download.
Note: This page no longer hosts the code it describes, but remains for documentation purposes. The latest version of this code can be downloaded here: Power Servoing Example for the NI PXIe-5644R
Note: The measurement techniques described in this document are patent pending.
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