Sampling Rate Conversion by Stages

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3.2.5 Sampling Rate Conversion by Stages

The decimator and interpolator discussed so far are of a single-stage structure. When large

changes in sampling rate are required, multiple stages of sample rate conversion are found

to be more computationally efficient. Most practical systems employ a multi-stage structure,

resulting in a considerable relaxation in the specifications of anti-aliasing (decimation)

or anti-imaging (interpolation) filters in each stage compared to a single stage realization.

The decimation in Figure 3.23 can be realized in two stages if the decimation factor

D can be expressed as a product of two integers, D₁ and D₂. Referring to Figure 3.24,

in the first stage, the signal x(n) is decimated by a factor of D1. The output, v(p) is

further decimated by D₂ in the second stage resulting in an overall decimation of x(n) by

                             Figure 3.23: Decimation in a Single Stage.

                              Figure 3.24: Decimation in Two Stages.

 

D = (D₁D₂). The filters H₁(z) and H₂(z) are so designed that the aliasing in the band of

interest is belowa prescribed level and that the overall passband and stopband tolerances are

met. This multi-stage sampling rate conversion system offers less computation and more

flexibility in filter design. An example is given below to illustrate the idea of multi-stage

sampling rate conversion.

Example: Multi-Stage Sampling Rate Conversion

We have a discrete time signal with a sampling rate of 90 kHz. The signal has the

desired information in the frequency band from 0 to 450 Hz (passband), and the band from

450 to 500 Hz is the transition band. The signal is to be decimated by a factor of ninety.

The required tolerances are a passband ripple of 0.002 and a stopband ripple of 0.001.

Decimation in a Single Stage

First we consider a single-stage design as shown in Figure 3.25(a). The specifications of

the required LPF are shown in Figure 3.25(b).

According to the formula by Kaiser, the approximate length of an FIR filter is given

by [34]

where peak passband ripple (linear) δ_p = 0.002, peak stopband ripple (linear) δ_s = 0.001,

normalized transition bandwidth  passband edge frequency fp = 450 Hz,

stopband edge frequency fs = 500 Hz, and sampling frequency F_s = 90 kHz.

From Equation 3.37, the lowpass FIR filter H(z) has a length of N ≈ 5424. Therefore,

the number of multiplications per second, M_sec, needed for this single-stage decimator is

Since only one out of ninety samples is actually used, the computation rate is based on the

decimated signal rate.

Decimation in Two Stages

Let us now consider the two-stage implementation of the decimation process as shown in

Figure 3.26.

Figure 3.25: (a) Block Diagram for Single-Stage Decimation, (b) The Filter Specification.

                    Figure 3.26: Block Diagram for Multi-Stage Decimation.

 

Due to the cascade decomposition, each of the two filters, H₁(z) and H₂(z), must have

a linear passband ripple specification half of that specified for the single-stage filter, H(z).

The stopband ripple specifications for these two filters can be the same as that of H(z)

since the cascade connection will only reduce the stopband ripple.

Stage One

The first stage will decimate the input signal x(n) by a factor of forty-five. The filter

specifications for the first-stage LPF H₁(z) are

                                            

                        Figure 3.27: Decimation Filter Design for Stage One.

                                     

These specifications are shown in Figure 3.27.

The reason for choosing this value of the stopband edge is that, after decimation by a

factor of forty-five, the residual energy of the signal in the band from 1000 to 2000 Hz will

be aliased back to the band from 0 to 1000 Hz. Due to the attenuation in the stopband, the

energy of the signal in the band from 1500 to 2000 Hz is very small compared to that in

1000 to 1500 Hz. So the amount of aliasing in the desired band of interest (0 to 450 Hz)

will also be small, resulting in very little signal distortion.

According to Equation 3.37, the approximate length of the FIR filter, H₁(z) is N₁ =

276. The number of multiplications per second for the first stage is

Stage Two

The specifications for the second-stage filter, H₂(z), are

                                  

Figure 3.28 shows the characteristics of H₂(z). This stage will perform a decimation

of factor two on the output signal of the first stage. So, the total decimation of x(n) is by a

factor of ninety as required.

                       Figure 3.28: Decimation Filter Design for Stage Two.

For the second stage, the length of the filter, as calculated from Equation 3.37, is N2 =

129. The number of multiplications required for this stage is

The total number of multiplications per second required for the two-stage implementation

of the decimator is

So, the two-stage implementation requires only    of the operation required of the

single-stage implementation

Decimation in Three Stages

To further illustrate the concept of multi-stage implementation of decimator and interpolator,

we will now consider the three-stage implementation as shown in Figure 3.29.

Stage One

In this stage, decimation by fifteen is performed on the input signal x(n). The characteristics

of the LPF, H₁(z), are shown in Figure 3.30. The filter specifications are

                                   

 

                                               

 

                         Figure 3.30: Decimation Filter Design for Stage One.

 

As in the two-stage case, the choice of stopband edge frequency can be extended to the

point for which negligible aliasing occurs in the passband (band of interest).

The approximate length of the filter as given by Equation 3.37 is N₁ = 60. The number

of multiplications per second for this stage is calculated as

Stage Two

In this stage, a decimation by a factor of three is done. The specifications of the LPF in this

stage, H₂(z), are

                                       

As before, the stopband edge frequency can be stretched out to 1500 Hz. The filter

characteristics are shown in Figure 3.31.

The length of filter required for this stage is N₂ = 20 and the number of multiplications

per second is

Stage Three

The third stage performs a decimation of factor two on the output of the second stage. The

specifications of the LPF, H₃(z), in this stage are

            

Figure 3.31: Decimation Filter Design for Stage Two.

                  

Figure 3.32 shows the specifications for H₃(z). As before, the approximate length of

the filter, as calculated from Equation 3.37, is N₃ = 134. The number of multiplications

required per second in the third stage is

                  Figure 3.32: Decimation Filter Design for Stage Three.

The total number of multiplications in the three stages of implementation is

[+] Enlarge Image

Compared to the single-stage implementation, the number ofmultiplicationsper second

are reduced by a factor of    by using three stages.

From this example, we can see that a significant saving in computation as well as in

storage can be achieved by a multi-stage decimator and interpolator design. These savings

depend on the optimum design of the number of stages and the choice of decimation factor

for the individual stages.

The examples illustrate the many different combinations and ordering possible. One

approach is to determine the sets of I and D factors that satisfy the filtering requirements

and then estimate the storage and computational costs for each set. The lowest cost solution

is then selected [37].

Relevant NI products

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