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The NI LabVIEW FPGA Module along with NI’s standard reconfigurable I/O (RIO) hardware has made field-programmable gate arrays (FPGAs) more accessible to engineers and scientists. However, a known difficulty with FPGA technology is overcoming the processor intensive task of synthesizing, placing, mapping, and routing an FPGA design, which results in compile times that last tens of minutes to hours. To further compound this problem, Moore’s law has resulted in larger, more complex designs that require longer compilations. Without action, the compile time will take over an increasingly large portion of the overall FPGA design process.
LabVIEW FPGA includes simulation and compilation capabilities, which help to accelerate your embedded system development process by verifying your design and off-loading the compilation to remote compilation farms. The new features of LabVIEW FPGA 2012 further drive your productivity with additional features to reduce compilation time and expand simulation support.
Fight the Trend of Increasing Compile Times
As an engineer or scientist, you may look at this LabVIEW FPGA design process challenge as a time equation, as illustrated in Figure 1. In an effort to reduce the amount of your time that you invest in finishing your project, you are looking to optimize the length of compilation and the number of compiles required.
Figure 1. Fight the trend of increasing FPGA compile times by reducing the multipliers of the total compile time equation.
A strategy to reduce the overall compilation time is to impact the two multipliers in the equation: reduce the number of compiles required by verifying your design first and/or reduce the compilation time itself. To assist in both of these strategies, NI has continued to invest in LabVIEW FPGA features by making further improvements in LabVIEW FPGA 2012.
Reduce the Compile Intervals: Verify Your LabVIEW FPGA Application First
To reduce the number of compile iterations, LabVIEW FPGA includes capabilities to verify your application logic both functionality and for timing before compilation.
Verify Your FPGA VI With Execution on a Development Computer
You can test the logic of an FPGA VI before compiling it by running the FPGA VI on a development computer with simulated I/O. When you run the FPGA VI on the development computer, you can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single stepping. To further exercise your design, create a test bench host VI to assert the FPGA inputs and monitor the FPGA I/O. In LabVIEW FPGA 2012, when you run your FPGA VI on your development computer, you will notice improved fidelity with respect to time when executing multiple single-cycle Timed Loops at the same or different clock rates and when sharing resources between two or more single-cycle Timed Loops.
Figure 2. Verify the logic of your LabVIEW FPGA VI by executing it on your development computer before committing to a compile.
LabVIEW FPGA also includes support for cycle-accurate simulation to gain an even higher fidelity of verification for your FPGA design before you commit to a compile.
Verify Your FPGA VI With Cycle-Accurate Simulation
Cycle-accurate simulators test both the logic and the timing constraints of your application by simulating the lower-level description of your LabVIEW FPGA code, which is generated by LabVIEW FPGA. These simulators also give you the ability to test your entire FPGA application, integrating your LabVIEW FPGA and Component-Level IP (CLIP) logic.
Traditionally, cycle-accurate simulators require you to create complex hardware description language (HDL)-based test benches to exercise your FPGA logic and read the I/O output. You can develop your cycle-accurate test benches faster with LabVIEW FPGA by creating a host VI to act as your test bench and drive the timing of your simulation by controlling the third-party cycle accurate simulator. This advanced functionality of LabVIEW FPGA is known as co-simulation. LabVIEW FPGA 2012 expands support of co-simulation with cycle-accurate simulators to now include the Mentor Graphics Questa Advanced Simulator.
Reduce the Time for One Compile: Offload Your Compile to Linux
It’s essential to verify your FPGA design on the development computer to avoid unnecessary compiles due to programming errors; however, in the end, compiling and testing in hardware are necessities. FPGA hardware testing is the ultimate fidelity simulation, as even the best cycle-accurate simulators cannot completely model every aspect of real-world behavior. To help this process, LabVIEW FPGA has a compilation architecture capable of off-loading compilation to dedicated computers either on-site in your office or to NI cloud compile servers.
Figure 3. Through a modular architecture, the LabVIEW FPGA compile system makes it easy off-load the processor intensive compilation process to dedicated computers either in your office or in the cloud.
Faster Compilations With Support for Linux
In LabVIEW FPGA 2012, you can iterate faster with new Linux-based FPGA compilation options. Linux-based compilation workers offer substantial performance benefits over Windows-based workers, reducing the compile time. For large, complex FPGA VIs, NI has seen a significant decrease in compilation times on the order of 20 to 50 percent; however, performance gains vary based on the specifications of the machine performing the compilation and the size of the FPGA target. Linux-based compilation is available with the zero-install, zero-maintenance LabVIEW FPGA Compile Cloud Service, or you can set up on your own in-house compilation servers.
Decreasing Your Total Compile Time
The secret to efficient FPGA development is to minimize the number and length of your compilations. LabVIEW FPGA 2012 continues to improve the FPGA design flow by providing higher fidelity logic verification and increased support for cycle-accurate simulators to conduct timing verification, before committing to a compilation. When you are ready to compile, LabVIEW FPGA 2012 introduces supports for Linux compilation that substantially reduces compile times for large, complex FPGA VIs.
Jonah Paul is a product manager for embedded software at National Instruments with a focus on real-time OS and FPGA-based embedded systems. He earned his bachelor’s degree in electrical engineering from the University of Wisconsin–Madison.
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