LabVIEW to the Pin – New Capabilities for Semiconductor Validation 

When first silicon of a new device arrives from fabrication, the options for testing the device are limited.    

Design or validation engineers can either rent time on the expensive, complex automated test equipment (ATE) systems that will eventually test the chip in production, or they can assemble the necessary equipment from benchtop instruments to confirm whether the actual silicon meets the functional requirements of the design.   

Both options introduce challenges. With ATE, the traditional vector-based approach to digital testing is breaking down as access to test points on systems on a chip or systems in a package becomes hidden. These more complex devices force a more system-level functional test, which is not the strength of conventional ATE. Benchtop instruments, on the other hand, have long excelled at system functional test and provide more relevant feedback in the design process, but it is virtually impossible to achieve the same in-cycle response or sheer test speed necessary for some device requirements.   

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Figure 1. Engineers can perform common parametric tests in the PXI platform by forcing and measuring voltage and/or current with high precision using the NI PXI-4130 SMU.  

Recent developments in the PXI platform and graphical system design provide an alternative to these two approaches for semiconductor validation, moving the capabilities of NI LabVIEW software even closer to each pin of a device. While the high-speed digital I/O capabilities of PXI have expanded over the years to rival the capabilities of the pin electronics in ATE, the DC sourcing capabilities have lagged. The new NI PXI-4130 source measure unit (SMU) represents a significant improvement in this area. Combining it with high-speed, high-channel switching solves most common parametric test problems. Graphical system design also provides the best method of testing the device in an emulation of its native environment. PXI field-programmable gate array (FPGA) modules and the FPGA Programming can often exceed the hardware-in-the-loop test capability of even high-performance ATE, and they abstract away the low-level chip details to offer a meaningful test of the device functionality as it was expected to be used. This delivers a solution to what is now being called “protocol-aware ATE,” or ATE that understands and emulates the intended use of the device, using PXI and LabVIEW to functionally verify chips in the same way engine control units have long been verified – in a recreation of their native environment.   

DC Parametric Measurements Using PXI  

Before verifying that the necessary stimuli to a chip yield the right response, a set of measurements are performed to validate the fabrication of the device itself. This often includes checking the performance of the CMOS transistors and protection diodes as well as overall current draw and leakage. These tests are often called “parametric” tests and include DC and AC characteristics. For the DC measurements, devices such as parametric measurement units (PMUs) or SMUs are required to force and measure current and voltage to the chip’s individual pins.

[+] Enlarge Image   Figure 2. As semiconductor devices become more complex, the methodology needed to test them more closely resembles system functional test than chip test. 

The PXI-4130 is a programmable, high-power SMU in a single-slot, 3U PXI module. The module has a single isolated SMU channel that offers a four-quadrant ±20 V output incorporating remote (4-wire) sense. With five available current ranges delivering source and measurement resolution down to 10 and 1 nA, respectively, this precision instrument can perform many of the standard DC parametric tests required for semiconductor devices, including the following:   

•          V_OH and I_OH  

•          V_OL and I_OL  

•          I_IL and I_IH  

•          I_DD gross, static, and dynamic

•          Shorted output current  

•          Opens and shorts   

Many of these tests use a test sequence similar to the following (for VOH):   

1. Put the device in an output-high state  

2. Force -4 mA from the SMU (the SMU acts as a load)  

3. Measure resulting voltage on the output pin – a fail occurs if it falls below 2.4 V   

Another key requirement for these DC measurements is a high-speed, high-lifetime switch module to connect the SMU to each pin. The recently released NI PXI-2535 and PXI-2536 544-crosspoint field-effect transistor (FET) matrix modules can connect the PXI-4130 SMU to hundreds of test points and switch at up to 50,000 cycles per second. Also, this switch uses FET technology, so it has no moving parts and therefore an unlimited lifetime – a key trait for a production system or even a durable validation station.   

These products add important capabilities to the PXI platform for making parametric measurements. Once finished with parametric tests, the chip validation generally proceeds with functional testing. For a simple digital device, this may involve sending multiple test vectors to the chip to run through a truth table to verify the proper outputs. As devices have become more complex with systems on a chip and systems in a package, though, the functional verification has had less access to individual components and has begun to include higher-level communication with the chip. To test a microcontroller, is it better to send a well-timed set of vectors while measuring expected response or simply boot it up and run some code on it? In this way, the chip test becomes more like the test of an assembled board, lending itself more toward a system functional test approach.   

“Protocol Aware” or “Mission Mode” Semiconductor Validation  

In the case of the microcontroller or even in a case where communication to the chip is through a protocol like SPI or I2C, the tester must be able to send and receive commands intelligently to the device, acting as both a talker and a listener. In the simplest sense, the tester should emulate the environment around the chip, testing the device as it was intended to be used (sometimes called mission mode). This is more than just having a list of patterns to generate expected results; rather, it is making decisions and reacting based on the patterns the tester receives. This often requires decisions to be made inside one timing cycle of the device. While protocol testers exist in benchtop instrument form, a more sophisticated solution is required for this level of interaction.   

Andrew Evans recently published a paper, “The New ATE – Protocol Aware,” at the 2007 International Test Conference (ITC) in Santa Clara, California, calling on silicon providers and ATE vendors to work together to meet this challenge. One excerpt states, “The missing item is the programmable logic that would be used for the emulation. This logic would primarily consist of FPGAs and would reside between the ATE pin electronics and the rest of the ATE pin, which is the vector memory, pattern/timing generators, and formatters.”   

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Figure 3. The LabVIEW Statechart Module represents SPI communication in a graphical manner by simplifying the deployment of code onto an FPGA for in-cycle response and offering an intuitive means of debugging failures.  

Graphical system design provides an intuitive methodology to simulate the native environment of the device in an FPGA: engineers can graphically design the system around the chip to emulate its surroundings. Consider the implementation of SPI communication using the LabVIEW Statechart Module with LabVIEW FPGA for the NI PXI-7831R R Series module. Embedding the SPI communication into an FPGA allows in-cycle response as a talker and listener for the chip.   

One way engineers can break down an SPI timing diagram into a state machine is to:   

1. Set ChipSelect low  

2. Set Data (0)  

3. Set Clock high  

4. Set Clock low  

5. Set Data (1)  

6. Set Clock high  

7. Set Clock low  

8. Repeat Data and Clock for bits 2 to 15  

9. Set ChipSelect high   

In this example, there are five unique steps, though some are repeated for each data bit. Figure 3 shows the LabVIEW statechart for the master device, or, in this case, the tester digital pin. Each of the steps listed above is broken down into five states in the statechart. Each state corresponds to setting or resetting one of the digital lines the FPGA is outputting.   

With statechart diagrams and graphical system design, engineers can build systems by defining states, transitions, and events. When debugging failures, engineers can then view errors by where they occur – which state, which transition, or during which event – in a graphical representation. This is similar to software developers preferring to debug a high-level language as opposed to viewing machine language, which would be similar to test vectors. Once created, engineers can deploy LabVIEW statechart diagrams directly to a PXI FPGA target to interface to the device under test. In this way, they can embed protocol intelligence or awareness behind each digital pin.   

More Intuitive Semiconductor Validation  

The PXI-4130 SMU and PXI-2535/36 switches, along with FPGA technology, deliver the power of LabVIEW closer to the pin to tackle parametric and functional validation tests in intuitive yet high-performance ways. Take advantage of these technologies to build a semiconductor validation system that combines the best traits of benchtop and production ATE systems.   

– Luke Schreier  

Luke Schreier is the group manager for precision DC and digital test. He holds a bachelor’s degree in mechanical engineering from the University of Nebraska – Lincoln.   

View technical resources on the new PXI-4130 SMU.  

This article first appeared in the Q1 2008 issue of Instrumentation Newsletter.

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