New Features in the LabVIEW FPGA Module 8.6
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This LabVIEW FPGA code is implementing a streaming FFT with windowing.
The latest version of the LabVIEW FPGA Module offers several new features for engineers and scientists including the following:
• Efficient Development and Debugging – NI LabVIEW FPGA code has always run on the development computer to simulate logic. Now, in Version 8.6, you can create custom data for I/O nodes and simultaneously run full behavioral host and FPGA VI simulations, including simulated DMA channels and read/write capability. With these enhancements, you can run your entire field-programmable gate array (FPGA) system, including the host VI, on the development computer with a test bench to exercise inputs and capture outputs for precompile behavioral verification.
• More Intellectual Property (IP) – FPGA palettes now include the highly requested fast Fourier transform (FFT) block, which can implement forward and inverse transforms with varying bin sizes and throughput levels. Nine options of windowing, divide, square root, rational resampling, new fixed-point functions, and an IP generator for adaptive filters are also available.
• Enhanced Fixed-Point Support – All inputs to FPGA IP blocks now support the fixed-point data type, including FIFOs and analysis VIs. Version 8.6 also features a mechanism to handle overflow within the data type.
• Complete Code Integration – With the new Component-Level IP (CLIP) Node, you can integrate any IP written in VHDL and run it independently of the enable chain for asynchronous execution and communication through user-defined I/O nodes.
• New Hardware Targets – NI is also releasing several new FPGA-enabled hardware targets, including the NI Single-Board RIO platform, new NI R Series PXI modules with Virtex-5 FPGA chips, and plug-in boards with direct access to FPGA pins.
View a webcast explaining the new features in more detail.
This article first appeared in the Q3 2008 issue of Instrumentation Newsletter.
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