Address Demanding Applications with FPGA-Enabled Instruments
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Push the envelope of high-performance test requirements with the NI LabVIEW FPGA Module and programmable instruments.
For demanding applications that require response times within a clock cycle, computation of large data sets, or extremely fast data transfers, virtual instruments can take advantage of user-accessible field-programmable gate arrays (FPGAs). Engineers can significantly optimize their test systems through continued advancements within the LabVIEW FPGA Module and PXI FPGA targets. Three test techniques in particular benefit from FPGA technology: custom triggering and data reduction, protocol-aware RFID testing, and coprocessing.
Custom Triggering and Data Reduction
One of the most useful applications for a user-programmable FPGA is on an instrument reducing the amount of data that must be sent back to the host for postprocessing, thereby freeing up the communications bus for other data transfers while reducing the burden on the CPU. Common methods for this include complex triggering, filtering, peak-detecting, or performing fast Fourier transforms (FFTs) on the instrument’s acquired data set.
Most instruments include some form of basic triggering capability, usually on a rising or falling digital edge or a specific analog level. Once the trigger threshold is reached, only the data of interest (pre- or post-trigger) is transferred. While many traditional instruments support specialized triggering modes, engineers are still limited by what the vendor adds to the instrument. Using the LabVIEW FPGA Module, however, highly customized triggers – such as Boolean combinations of triggers on multiple inputs or sequential triggering and serial pattern matching – become straightforward. Through custom triggering, engineers can add enhanced granularity to their window of interest, further reducing the amount of data to transfer.
Figure 1. The FPGA on the NI PXIe-5442 module performs quadrature digital upconversion to reduce data transfers and increase signal playback time.
Another method for data reduction on communications signals involves digital upconverters (DUCs) and digital downconverters (DDCs). NI offers DUCs and DDCs on enhanced versions of arbitrary waveform generators, digitizers, and RF vector signal analyzers and generators. For example, the NI PXIe-5442 16-bit, 100 MS/s arbitrary waveform generator quadrature DUC capability takes I and Q complex waveform data and, with the help of onboard signal processing in the FPGA, interpolates the baseband signal and upconverts the data to a carrier frequency of up to 43 MHz. Performing this processing in hardware rather than software results in dramatically faster waveform computation and smaller sizes, saving waveform download time and providing longer playback time. This improves the statistical significance of many measurements and visualizations such as bit error rate, trellis plots, and constellation plots.
Protocol-Aware RFID Testing
As semiconductor devices become more complex, previous test methods (standard digital test vectors) are becoming difficult, even impossible. This is especially true within devices that expose their functionality not through parallel digital pins but rather through serial or wireless protocols often requiring master and slave responses within a clock cycle. The complexity has led to the demand for “protocol-aware ATE,” or test equipment’s knowledge of the communications protocols within which the device operates and onboard processing to accommodate timing requirements.
Figure 2. The link timing requirements (T1, T2, T3, and T4) for RFID tags force decision making to occur in hardware rather than the host.
With an RFID tag, for example, there are no physical access points to probe, so the only way to communicate with the device under test (DUT) is through a wireless protocol. Also, RFID standards specify minimum and maximum response times. Therefore, the process of testing these devices requires full emulation of the test sequence in hardware to meet the timing requirements. Figure 2 represents a typical RFID tag test sequence, with the tester functioning as the interrogator.
Through a sequence of commands sent and received between both devices, an RFID reader can identify the electronic product code (EPC) of an RFID tag. However, sending the data from the tag through a measurement system and back to the host does not meet the timing requirements (microseconds) demanded by this system. When engineers can run the intelligence for coding/decoding, modulation/demodulation, and more on a LabVIEW FPGA target inside the measurement system, the timing is well within range. The NI PCI-5640R IF-RIO transceiver has the necessary A/D and D/A converters (14 bits, 20 MHz real-time bandwidth), DUC and DDC capabilities, as well as FPGA space to include decision making for the RFID tag test. When engineers pair the PCI-5640R with RF upconverters or downconverters, they can perform these tests in the HF (13.56 MHz), UHF (850 to 950 MHz), or microwave (2.40 to 2.45 GHz) ranges depending on their DUTs.
Figure 3. With new fixed-point math capabilities in the LabVIEW FPGA Module, coprocessing applications involving FFTs can exist on PXI FPGA targets for increased performance.
Coprocessing
For very complex data manipulation and signal processing, it is often necessary to dedicate processing power to this task alone. Multicore controllers provide one suitable avenue for this, but for the ultimate in parallel processing, it is difficult to surpass the capability of an FPGA. With intense signal or image processing applications and real-time rendering requirements using multiple FFTs, a sequential processor struggles. Using the new fixed-point math capability of the LabVIEW FPGA Module and the available FFT intellectual property (IP) on ni.com/ipnet, an engineer can place up to eight parallel FFT operations onto the Virtex-5 LX50 FPGA of the NI PXI-7842R R Series module. With the dedicated bandwidth of PXI Express (up to 1 GB/s per direction) and peer-to-peer streaming on the horizon, this type of capability is of increasing value in future test systems.
Luke Schreier is the modular instruments group manager at National Instruments. He holds a bachelor’s degree in mechanical engineering from the University of Nebraska – Lincoln.
View more information on improving test methods with FPGAs.
This article first appeared in the Q3 2008 issue of Instrumentation Newsletter.
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