Table of Contents
Description
Asynchronous reset refers to a camera feature that allows the camera to output a frame immediately upon receipt of a trigger. Without asynchronous reset capability, the frame grabber would have to wait for the camera to finish outputting the current frame before acquiring the next full frame. Asynchronous reset is a mode associated with the camera. The frame grabber is not concerned with whether the camera resets or not; it just uses the signals output by the camera to determine when a frame is being sent. The IMAQ PCI/PXI-1408, however, must be operated in External Lock mode in order to work with a camera in asynchronous reset mode. External Lock mode requires the camera to provide a horizontal sync (HSYNC), vertical sync (VSYNC), and pixel clock (PCLK) to the frame grabber. With other operating modes, the frame grabber generates the PCLK signal internally. The circuitry that produces the PCLK signal requires several HSYNC pulses to lock onto the timing signals and generate the PCLK. This is impractical in asynchronous reset mode, since the idea is to acquire a frame immediately upon receipt of a trigger. Configure External Lock mode using Measurement & Automation Explorer's IMAQ configuration utility. You can find the External Lock setting under the Operating Mode tab of the PCI-1408 or PXI-1408 properties window, as shown below:

The PCI/PXI-1408 does not provide a serial interface for camera control, so you must ensure that the camera is set to asynchronous reset mode by other means. Two methods are as follows:
What To Expect
Capture of a short duration event.
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