Integrating a Model from Xilinx SystemGenerator for DSP into LabVIEW FPGA

Introduction

The increase in consumer demand for electronic devices in recent decades, has meant that engineers who design, prototype, deploy, and test these new devices need the shortest product development cycle as possible, along with a scalable software platform for use throughout their design cycle. In addition to the built-in programming capabilities of LabVIEW FPGA, Xilinx SystemGenerator for DSP is a software package that may be used in conjunction with LabVIEW to achieve ultra-fast digital signal processing (DSP) on NI-RIO (Reconfigurable I/O) hardware devices. Since NI-RIO devices feature Xilinx Virtex-II FPGAs, leveraging pre-optimized DSP algorithms designed specifically for the Xilinx family of FPGA’s is an option that can enhance the signal processing capabilities of LabVIEW FPGA.

This application note describes the general process of taking a Xilinx SystemGenerator DSP model and importing that into the LabVIEW FPGA Module using the HDL Interface Node. This brings advanced and ultra-fast DSP algorithms to NI-RIO devices.

Software and Hardware Requirements

The following software versions and hardware are required to use Xilinx System Generator for DSP with LabVIEW FPGA:
When importing a SystemGenerator model into LabVIEW FPGA, one of the main considerations is to carefully synchronize the Simulink system period of the SystemGenerator model with LabVIEW FPGA. The Simulink system period, in units of seconds, is the greatest common divisor of the sample periods that appear in the model. This becomes important when understanding the input-output relation of a model in SystemGenerator.

The clocked process we will consider is a “4 Channel FIR Filter.”

4Channel FIR Filter

This design implements a 4 channel FIR filter where the input data rate is relatively slow compared to the
processing clock, and each channel uses the same filter coefficients. Main features are:
· The filter length = 128 taps.
· The coeff bit width 12 bit, 0.sxxx xxxx xxxx format, max absolute coeff is 0.5.
· The relationship of processing clk (pclk), data sampling rate(fs), number of tap (nof_tap), number of channel (nof_chan) is:
o fs = pclk/(nof_chan*nof_tap), for ex: for pclk=24.62MHz, nof_tap=128, nof_chan=4, fs=48.1KHz.
o Note that by decreasing the number of taps, the number of channels can increase for the same data sampling rate.
· The design utilizes the dual port block RAM for storing the data samples and coefficients, to save FPGA slice count
· The design uses only a single multiplier and adder. There is no truncation at the output of multiplier and adder the output carries the full bit-width word out of the MAC.

Since our goal is to import this pre-optimized DSP algorithm into LabVIEW FPGA without modifying the model itself, we can immediately generate the VHDL code from this model. There are different ways in which System Generator can compile your design into an equivalent, lower level, representation. The representation that is recommended for use with LabVIEW FPGA is the NGC Netlist compilation type. This compilation type allows you to compile your design into a standalone Xilinx NGC binary netlist file. This netlist file is saved as <design>_clk_wrapper.ngc in the design's target directory, where <design> is derived from the portion of the design being compiled. The NGC netlist file that System Generator produces contains both the logical and constraint information for your design.

The SystemGenerator settings are accessed by double-clicking the SystemGenerator block. The settings used in this example are the following:
· Compilation: NGC Netlist
· Part: Virtex2 xc2v1000-4fg456 (note: applicable for 1 million gate NI-RIO devices)
· Target Directory: (your directory)
· Synthesis Tool: XST
· Hardware Description Language: VHDL
· FPGA Clock Period (ns): 25
· Clock Pin Location: N/A
· Override with Doubles: According to Block Settings
· Simulink System Period (sec): 1/512

The key setting is the Simulink System Period: 1/512, which defines
the input to output relationship of the model to 512 ticks.

After selecting “Generate” from the System Generator settings dialog box, the NGC Netlist and related files will be created. Although many files are created, the only two files that will be needed to integrate into the HDL Interface Node of LabVIEW FPGA are:
1. “macfir_4ch4_slow_r13_clk_wrapper.vhd”
2. “macfir_4ch4_slow_r13_clk_wrapper.ngc”

LabVIEW FPGA Procedure

The LabVIEW FPGA procedure consists of three steps:
1. Sample an analog input channel of the NI-RIO device, in this case a PXI-7831R board. Alternatively, a sine wave may be generated in software to simulate data. This signal is considered the "Pre-Process Signal" which we will run through the DSP algorithm.
2. The next step is to import the NGC Netlist created by the SystemGenerator model “4 Channel FIR Filter.” This is the key step of the application, which accomplishes our goal of performing the signal processing using a pre-optimized algorithm designed by Xilinx.
3. Finally, we will output the signals to the analog output channels of the PXI-7831R (Post-Process Signal).

The following block diagram shows LabVIEW FPGA code used to implement this design.


In general, the HDL Interface Node in LabVIEW FPGA can be used in two main ways:
1) To insert HDL code directly into LabVIEW FPGA (without calling external files). For more information, refer to the document “Importing HDL Code into FPGA VI’s Using the HDL Interface Node.”
2) As a wrapper to call an intellectual property (IP) core or algorithm from an external source file. For more information, refer to the document "Integrating IP Cores into LabVIEW FPGA with the HDL Interface Node."

This application used the HDL Interface Node as a wrapper to call the NGC Netlist created by the “4 Channel FIR Filter” SystemGenerator model.

Before looking at the lower-level HDL code that makes up the wrapper, it’s helpful to understand at a higher-abstraction how the wrapper connects the “Pre-Process Signals” from LabVIEW FPGA to the HDL Node, and then outputs the “Post-Process Signals.” First, the signals are connected from the LabVIEW block diagram to the HDL Interface Node inputs (LVdin1, 2, 3, 4). These inputs are then directly connected to the inputs of the “4 Channel FIR Filter” model component. During the signal processing, outputs of the model are passed to intermediary signals (int_dout1, 2, 3, 4) to register the outputs until the algorithm is complete (recall that the input to output relationship of the model is 512 clock ticks). When 512 ticks have passed, a ready (rdy) signal is asserted which can be visualized as the first column of digital switches, to allow the intermediary signals further down the execution path. Finally, the next rising clock edge will assert an enable_out signal (visualized in the diagram, as the second column of switches) to pass the data all the way to the HDL Interface Node Outputs (LVdout1, 2, 3, 4). At that time, LabVIEW can collect the outputted data.

The HDL Interface Node has six configuration tabs: Parameters, Code, Emulation, External Files, Execution Control, and Simulation.

Parameters

Since connections cannot be made from LabVIEW FPGA directly to the inputs of the component from the SystemGenerator model, parameters must be used to go between the two. Since the “4 Channel FIR Filter” model requires four inputs and four outputs, similarly we will create four input parameters and four output parameters.


Code

There are four sections in the Code tab of the HDL Interface Node: Libraries, Entity, Architecture, and Begin.

The Libraries declared in this example are:
“library IEEE; use IEEE.std_logic_1164.all;”
“library IEEE; use IEEE.std_logic_arith.all;”

The Entity section is automatically created and defines the parameters entered in the parameter tab.

The Architecture portion of the code may be found in the .VHD file generated by System Generator, in this example the filename is “macfir_4ch4_slow_r13_clk_wrapper.VHD”. The portion of this file that must be copied is highlighted in the Figure shown below. Since we are instantiating this as a component, be sure to change the keyword “entity” to “component”. Additionally, the following signals are defined in this section of the code:
· signal rdy: std_logic;
o This signal will be asserted after count reached the desired number of tick clocks.
· signal count: integer;
o This signal increments each clock tick until reaching 511 and resetting, which is the period defined in Simulink for this particular model.
· Signal int_dout1, int_dout2, int_dout3, int_dout4: std_logic_vector(31 downto 0);
o These are intermediate signals that will connect the outputs from the System Generator model (data1, 2, 3, 4) to the parameters LVdout1, 2, 3, 4.


The final section of code is under the Begin heading. This is where functionality defined by the SystemGenerator model is executed.

External Files

The External File tab is where the NGC Netlist of the SystemGenerator model is imported.

The naming convention of the NGC Netlist generated by SystemGenerator to import in LabVIEW FPGA is the following: “<design>_clk_wrapper.ngc”

Execution Control

Since this example does not use the HDL Interface Node in a Single-Cycle Timed Loop, Single-Cycle Timed Loop Not Allowed on the Execution Control tab is selected.

Note: This example does not perform emulation or simulation, so both of these tabs are left blank.
This concludes all the requirements to import a Xilinx SystemGenerator for DSP model into LabVIEW FPGA. The two main considerations discussed were the following:
1. The input-output relationship of the SystemGenerator model (in this case, 512 clock ticks)
2. How to make the necessary connections to use the HDL Interface Node as a wrapper for the SystemGenerator model.

For more information, please refer to the documents listed below in the Related Links.
Related Links:
HDL Interface Node FAQ
Importing HDL Code into FPGA VIs Using the HDL Interface Node
Integrating IP Cores into LabVIEW FPGA with the HDL Interface Node

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