Common Terminology and Definitions for Digital I/O and Logic Analyzers

This tutorial is part of the National Instruments Measurement Fundamentals series. Each tutorial in this series, will teach you a specific topic of common measurement applications, by explaining the theory and giving practical examples. This tutorial covers the common terminology and definitions for digital I/O and logic analyzers.

For additional digital only concepts, refer to the Digital I/O Fundamentals main page.
For the complete list of tutorials, return to the NI Measurement Fundamentals Main page.

Jitter

Jitter is the deviation from ideal timing of an event, and is typically measured from the zero-crossing of a reference signal. Jitter typically comes from cross-talk, simultaneous switching outputs, and other regularly occurring interference signals. Since jitter varies over time, measurements and quantification of jitter can range from a visual estimate on a scope of the range of jitter in seconds, to a statistical-based measurement such as one based on the standard deviation over time. For clocked (dynamic) generation, channel-to-channel skew is defined as the time difference between corresponding edges on the data channels. For example, if two data channels are each programmed to transition from low to high level on a particular sample, the time difference between the rising edges on the two channels would be the channel-to-channel skew between the two channels.

For dynamic acquisition, channel-to-channel skew is defined as the difference between the sampling times for each data channel. When each sample is acquired, the point in time at which each data channel is sampled with respect to every other data channel is not identical, but the difference is within some small window of time. This time window is referred to as the channel-to-channel skew.

The following figure shows the channel-to-channel skew of a group of signals.

Specified channel-to-channel skew generally refers to the skew across all data channels on a device.

Rise time and fall time

Rise time (t_rise) is the time that it takes a signal to rise from 20% to 80% of the voltage between the low level and the high level. Fall time (t_fall)is the time that it takes a signal to fall from 80% to 20% of the voltage between the low level and the high level. Preshoot and overshoot are peak distortions preceding (preshoot) or following (overshoot) an edge. Figure 4 shows an example of preshoot and overshoot on a signal.

Note: Together, overshoot, preshoot, and undershoot are called aberrations.Settling time (t_S) is the time required for an amplifier, relay, or other circuits to reach a stable mode of operation. In the context of signal acquisition, the settling time for full-scale step is the amount of time required for a signal to reach a certain accuracy and stay within that accuracy range.
For clock signals, the percentage of the waveform period that the waveform is at logic high level. The following figure shows the difference between two waveforms with different duty cycles. Notice that the 30% duty-cycle waveform is at logic high level for less time than the 50% duty cycle.
Hysteresis refers to the difference in voltage levels between the detection of a transition from a logic low to a logic high and the transition from a logic high to a logic low. Refer to figure 7 for a diagram illustrating hysteresis.

All digital logic devices have some level of hysteresis on their digital inputs. The magnitude of a particular device's hysteresis can be determined by:

Hysteresis ≈ V_IH - V_IL

On a rising edge of the digital signal on the input, the device detects a transition from a logic low to a logic high at V_IH. Conversely, the device detects a transition from a logic high to a logic low when the voltage at the input of the device crosses V_IL.

Hysteresis is a very useful property for digital devices because it naturally provides some amount of immunity to high-frequency noise in your digital system. This noise, often caused by reflections from the high edge rates of logic level transitions, could cause false transition detections by the digital device if only a single voltage threshold determined a change in logic state. This phenomenon is more clearly illustrated in figure 8.

In this figure, the first sample is acquired as a logic low level. The second sample is also a logic low level because the signal has not yet crossed the high level threshold. The third and fourth samples are logic high level, and the fifth is logic low level.

For devices with fixed voltage thresholds, the noise immunity margin (NIM) and hysteresis of your system are determined by your choice of system components. For example, some NI digital I/O devices give you the ability to control both your system NIM and hysteresis. Both system NIM and hysteresis give your system levels of noise immunity, but for a specific logic family, there is always a trade-off between these two—the larger the hysteresis, the smaller the NIM, and vice versa. To determine how to set your voltage thresholds, you should carefully examine the signal quality in your system to determine whether you need more noise immunity from your high and low logic levels (greater NIM) or need more noise immunity on your logic level transitions (greater hysteresis).

Relevant NI Products

Customers interested in this topic were also interested in the following NI products:

• High-Speed Digital I/O
• Industrial Digital I/O
• Logic Analyzers
• Modular Instruments (digital multimeters, digitizers, switching, etc...)
• Digital Waveform Editor
• LabVIEW Graphical Programming Environment
• SignalExpress Interactive Software Environment

For the complete list of tutorials, return to the NI Measurement Fundamentals Main page

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