Creating a Custom FPGA VI For Use With Simulation Interface Toolkit 3.0.x

The LabVIEW Simulation Interface Toolkit (SIT) 3.0.x ships with a default FPGA VI (LabVIEW 7.1.x) or bitfile (LabVIEW 8.0.x and later) for all National Instruments R Series Intelligent DAQ devices. These default VIs and bitfiles include the most common I/O configurations for each device, including digital inputs and outputs, pulse width modulator (PWM) inputs and outputs, and, in the case of the 783x R Series devices, analog inputs and analog outputs.

These default VIs and bitfiles are sufficient for many applications using R Series devices. However, in some situations, you might need to create a custom FPGA VI to use with a simulation. For example, if you want additional digital I/O lines, more than two pulse width modulator outputs, or digital filtering built into the FPGA, you must create a custom FPGA VI.

Additionally, if you want to run a simulation using a CompactRIO (cRIO) device, you must create a custom FPGA VI. The I/O of the cRIO platform is defined completely by the user and any C-Series modules in the cRIO chassis.

This document explains how to create a custom FPGA VI for SIT 3.0.x in both LabVIEW 7.1.x and LabVIEW 8.0.x.

Starting From a Default SIT FPGA VI

The first step is to modify a copy of a default FPGA VI.

LabVIEW 8.0.x

R Series Devices:

1. Browse to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
2. Create a copy of sitfpga master.lvproj, and place this copy in this same directory.
3. Open this copy in LabVIEW.
4. Expand the RT PXI Target (0.0.0.0) item in the Project Explorer window.
5. Expand the PXI-7831R (PXI-7831R) item in the Project Explorer window.
6. This example project was created with a PXI-7831R device as the target in a real-time PXI system. If you are using a different R Series device or a PXI-7831R device with a Windows based PXI controller, you must create a new FPGA target for your device. If you are using a PXI-7831R with a real-time PXI controller (the default for the example project), skip to step 7. Otherwise, complete the following steps to add a new R Series FPGA target to the project.
   1. Right-click the target that controls the R Series device and select New»Targets and Devices from the shortcut menu. This target is My Computer if you are using a Windows-based desktop PC or PXI controller. This target is RT PXI Target (0.0.0.0) if you are using a real-time PXI controller.
   2. Select the New target or device option in the Targets and Devices dialog box.
   3. Select the R Series device type from the list, and click the OK button.
   4. Click and drag sitfpga master.vi from the PXI-7831R target to the new R Series target.
7. Double-click sitfpga master.vi in the Project Explorer window.
8. Select File»Save As from the pull-down menu.
9. Ensure the Substitute copy for original option is selected and click the Continue button.
10. Rename the VI and save it to the same directory as in Step 1.
11. Save the project by clicking the Save button in the Project Explorer window.
12. Create the FPGA I/O for the R Series target. This project defines the FPGA I/O for the PXI-7831R as follows: analog input channels 0-7, analog output channels 0-7, and digital lines 0-31 on both connectors 1 and 2. If you created a new R Series target in step 6, you can drag the FPGA I/O folders from the original PXI-7831R target to the new R Series target. The FPGA VI shows broken wires from any FPGA I/O Node items whose channels are undefined.
    
    For information about creating FPGA I/O items for projects, refer to the FPGA Module topic of the LabVIEW Help. Depending on the R Series device and the project needs, you might need to add more or less FPGA I/O. For example, the PXI-7811R device has 160 DIO lines available; however, by default this project defines only the first 32 lines on connectors 1 and 2. You can add more FPGA I/O to this project if you want to use the additional DIO lines available on the PXI-7811R. Conversely, the PXI-7811R has no analog inputs or outputs, so if you are using this device, you can remove the analog I/O from the project. You also can remove the corresponding FPGA I/O Nodes from the VI.

The next step is modifying the FPGA VI to create a custom FPGA VI for the SIT project. Skip to the Rules for Creating a Custom SIT FPGA VI section of this document.

CompactRIO Systems:

1. Browse to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
2. Create a copy of sitfpga cRIO master.lvproj, and place this copy in this directory.
3. Open this copy in LabVIEW.
4. Expand the FPGA Target (cRIO-9103) item in the Project Explorer window.
5. This example project was created with a cRIO-9103 as the target. If you are using a different chassis, you must create a new FPGA target for this chassis. If you are using a cRIO-9103 chassis skip to step 7. Otherwise, complete the following steps to add a new cRIO chassis to the project.
   1. Right-click the RT CompactRIO Target (0.0.0.0) item and select New»Targets and Devices from the shortcut menu.
   2. Select the New target or device option in the Targets and Devices dialog box.
   3. Select the cRIO chassis type from the list, and click the OK button.
6. Copy the files sitfpga cRIO master.vi and sitfpga cRIO calibration 8_0.llb to the newly created cRIO chassis target by clicking and dragging these files from the FPGA Target (cRIO-9103) target to the new chassis target.
7. Double-click sitfpga cRIO master.vi in the Project Explorer window.
8. Select File»Save As from the pull-down menu.
9. Ensure the Substitute copy for original option is selected and click the Continue button.
10. Rename the VI and save it to the same directory mentioned in Step 1.
11. Save the project by clicking the Save button in the Project Explorer window.
12. Create the cRIO FPGA I/O for this project. The example FPGA Target (cRIO-9103) in sitfpga cRIO master.proj defines an NI 9215 module for analog input, an NI 9263 module for analog output, an NI 9411 module for digital input, and an NI 9474 module for digital output. If you created a new cRIO chassis target in step 5, add the C Series modules you will be using in your project by right-clicking on the new cRIO chassis target and selecting New»C Series Modules.... If you have a cRIO-9103 chassis and are still using the example FPGA Target (cRIO-9103) defined by the project, you might want to delete the existing C Series modules and FPGA I/O. Then, define the correct C Series modules and FPGA I/O for the specific modules and channels this project uses.
    
    For information about adding C Series modules and FPGA I/O to projects, refer to the FPGA Module book of the LabVIEW Help. Note that in the sitfpga cRIO master.vi example, the FPGA itself calibrates the analog input and analog output channels of the NI 9215 and NI 9263 modules. The host VI running on the cRIO real-time controller typically performs this calibration. For examples about doing channel calibration on the real-time host side rather than on the FPGA itself, refer to the NI-RIO shipping examples Analog Input - cRIO.lvproj and Analog Output - cRIO.lvproj. These examples are availably by launching LabVIEW and selecting Help»Find Examples from the pull-down menu.

The next step is modifying the FPGA VI to create a custom FPGA VI for the SIT project. Skip to the Rules for Creating a Custom SIT FPGA VI section of this document.

LabVIEW 7.1.x

1. Browse to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
2. SIT 3.0.x ships with a default master and slave FPGA project file (.lep) and FPGA VI for each R Series device for both LabVIEW 7.1 and LabVIEW 7.1.1. SIT SIT 3.0.x also ships with two example FPGA project files and VIs for cRIO; one each for LabVIEW 7.1 and LabVIEW 7.1.1. These project files and VIs are compiled for a cRIO-9103 chassis. Open the FPGA project file that corresponds to the version of LabVIEW that you are using, the R Series device the project uses, and whether the device is the master or slave. In the case of cRIO, open the cRIO project that corresponds to the version of LabVIEW that you are using.
3. Display the Embedded Project Manager window and select File»Save Project As from the pull-down menu. Choose a name for the project and save it in the same directory as in Step 1.
4. In the Embedded Project Manager window, double-click the FPGA VI associated with the project to open this VI.
5. Select File»Save As from the pull-down menu and save the VI with a new name. NOTE: SIT relies on a naming convention to properly identify FPGA VIs. Do not modify this convention; you must only append a custom name to the current name. For example, the default SIT master VI for the PXI-7831R device for LabVIEW 7.1.1 is named sitfpga PXI-7831R 7_1_1 master.vi. To customize this VI, you must leave everything intact but add a custom name to the end. For example, you could name this VI sitfpga PXI-7831R 7_1_1 master custom_name.vi. When creating custom FPGA VIs for CompactRIO, you must follow this convention, replacing cRIO-9103 with whatever cRIO chassis you have. For example, if you have a cRIO-9104 chassis, you can name the FPGA VI sitfpga cRIO-9104 7_1 master my_custom_SIT_project.vi. If you are using LabVIEW 7.1.1, the 7_1 in the file name must be 7_1_1.
6. If you have not already done so, select Target»Switch Execution Target»<FPGA target> from the pull-down menu, where <FPGA target> is the name of the FPGA device for which you are compiling this VI. This action targets LabVIEW to the appropriate FPGA device.
7. Save the project by selecting File»Save from the Embedded Project Manager window.
   
   For more information about the Embedded Project Manager or targeting FPGA devices, refer to the FPGA Module book of the LabVIEW Help.
   

The next step is modifying the FPGA VI to create a custom FPGA VI for the SIT project. Skip to the Rules for Creating a Custom SIT FPGA VI section of this document.

Rules for Creating a Custom SIT FPGA VI

Now that you have created a copy of a default SIT FPGA VI, the next step is to modify this VI to meet the needs of the project. You also can add analog or digital input or output channels, additional PWMs, counters, digital filtering, or other components to the FPGA VI.

While you are modifying the FPGA VI, pay attention to the following guidelines to ensure the SIT Connection Manager dialog box recognizes this FPGA VI. You use this dialog box to create mappings between model I/O and FPGA device I/O.

1. Do not remove or rename the input loop, output loop, loop timers, or the _use RTSI boolean control. Also, do not remove or rename any IRQs the VI uses for host/target synchronization.
2. Do not modify, remove, or rename any controls or indicators shown in Figure 1. However, you can rename or remove the PWM I/O if you do not need them.
3. As you create controls and indicators to represent FPGA I/O, do not begin the name of these new objects with an underscore. The SIT Connection Manager dialog box filters out any objects with an underscore at the beginning of the name. Conversely, if you want use a control or indicator as an intermediate value, such as those in the PWM I/O loops, prepend an underscore to the name of these objects. This underscore ensures the user does not see the object as available for a mapping.
4. Any additional PWM input or output controls or indicators must follow the same naming convention as the default FPGA VI. For example, the two default PWM input controls are named PWM in 0 (C 0 DIO 0) and PWM in 1 (C 0 DIO 1). A third PWM input should be named PWM in 2 (C <connector number> DIO <DIO line number>). The easiest way to add additional PWM inputs or outputs is to copy and paste the code for the PWM input or output and renaming the object appropriately.

When you are finished creating the FPGA VI, select File»Save from the pull-down menu to save this VI.

Rules for Naming and Placing the Compiled FPGA VI or Bitfile

If you are using LabVIEW 8.0.x, the next step is compiling the FPGA bitfile. If you are using LabVIEW 7.1.x, the next step is compiling the FPGA VI. Refer to the appropriate section below based on the version of LabVIEW you are using.

LabVIEW 8.0.x

Complete the following steps to compile the bitfile for the FPGA VI you created.

1. Display the Project Explorer window.
2. Right-click the FPGA VI in the tree and select Compile from the shortcut menu to compile the bitfile for this VI.
3. Ensure the bitfile is in the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\FPGA Bitfiles\ directory. The Xilinx compiler places the bitfile here automatically if the project file is located in the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
4. Rename the bitfile to follow SIT naming convention. By default, the bitfile name is <name of project>_<name of FPGA>.lvbit. You must rename this file as follows: sitfpga <FPGA_device> <LV_version> type custom_name.lvbit, where type is master or slave and custom_name is a name you specify. For example, the master bitfile for the NI PXI-7831R is named sitfpga PXI-7831R 8_0 master.lvbit. Note that SIT 3.0.1 only ships with one bitfile for cRIO named sitfpga cRIO-9103 8_0 master.lvbit. When creating your custom FPGA VIs for CompactRIO you need to follow this same naming convention, replacing cRIO-9103 with whatever cRIO chassis you have. For example, if I had a cRIO-9104 chassis I could name my Bitfile sitfpga cRIO-9104 8_0 master my_custom_SIT_project.lvbit.

LabVIEW 7.1.x

Complete the following steps to compile the FPGA VI you created.

1. Display the Embedded Project Manager window and select Target»Build to compile the VI.
2. Ensure the FPGA VI is located in the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory. The Xilinx compiler places the FPGA VI here automatically if the project is located in the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs directory\.
   

   Using the Custom FPGA VI with the SIT Connection Manager
   

After you have compiled the bitfile or FPGA VI, the next step is using the SIT Connection Manager dialog box to create a mapping between the model DLL and the FPGA device. For instructions on creating these mappings, refer to the Creating Mappings for National Instruments FPGA Devices topic of the LabVIEW Help .

NOTE: If you are using LabVIEW 7.1.x, this help is available by selecting Help»Simulation Interface Toolkit Help from the pull-down menu. If you are using LabVIEW 8.0.x, this help is available by selecting Help»Search the LabVIEW Help and navigating to the Toolkits»Simulation Interface Toolkit book.

As you work through the tutorial located in this help topic, notice that SIT enables the Browse button on the Add FPGA Device dialog box. When you click this button, you can specify the custom FPGA VI or bitfile you created. You then can create mappings between the model DLL and the FPGA device associated with this VI/bitfile. Figure 2 shows this process.
This tutorial assumed use of a single R Series device. You can use more than one FPGA device in your simulation, with one of the R Series devices acting as the master device and any others acting as slaves. If you use multiple FPGA devices, you must have a bitfile for each device. Depending on the architecture of the project, you might not need to use a custom FPGA VI for the slave FPGA devices. If the slave devices also need to use a custom FPGA VI, repeat the steps listed in this tutorial for the custom slave FPGA VIs, but instead of starting with the default master FPGA project files, start with the default slave FPGA project files.

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