Developing a Hardware-Timed Batch Process System with CompactRIO

In this document you will learn how to use the LabVIEW FPGA Module and CompactRIO to implement a monitoring and control system for a hardware-timed batch process. This document presents a general approach that you can use to develop these types of applications. Different techniques are discussed that will help you develop a successful CompactRIO application.

Determining the Requirements of the Application

Whenever you are starting to work on a new project or application, you must identify, evaluate, and prioritize the requirements of the application in order to determine the platform that will best suit your application.

Type of Signals That Will be Measured
The first step is to determine what type of signals will be measured, analog or digital, and what the environment around the signals will be. Also, knowing the range of these signals will help you choose the platform for your application. For example, if you are reading temperature using a thermocouple, you need to provide signal conditioning to effectively measure the mV signal and then convert it to some units of degrees. Or you might have a ±24 V digital output signal that will be controlling a relay or an ON-OFF switch. You might even have a signal coming out of a transducer (pressure, flow, temperature) in the form of 0–20 mA. If you are planning to implement a solution that contains only one type of these signals, or a combination of them, you should consider a platform that is capable of providing the signal conditioning necessary to easily and accurately measure them.

CompactRIO features a wide variety of different industrial I/O modules that provide signal conditioning for most application needs. In most cases, you can directly connect a sensor or actuator to the module. For example, the cRIO-9211 module provides connectivity to thermocouples, 24-bit resolution, and includes Cold Junction Compensation (CJC) and autozero functionality. Linked below is the CompactRIO page on the National Instruments Web site that provides detailed information about the I/O modules available for signal conditioning and connectivity.

Speed of the Application
Depending on the application you are developing, you may have requirements for speed of acquisition or control. With the LabVIEW FPGA Module and CompactRIO, you can achieve hardware-timed computational rates up to 40 MHz. Typically, the FPGA circuitry is faster than the I/O rate of the modules. Since the LabVIEW code is actually running in silicon hardware, and no operating system is involved in the process of running your code, the determinism of the application is at the highest level. This is a key factor for applications that need to have a very fast response when doing process control, digital communication protocols, or customized triggering.

For most applications, some level of control, processing, and analysis needs to be performed, which has an effect on the speed of the application. With CompactRIO, you have the ability to implement certain portions of your application in FPGA hardware and may also choose to implement other portions of the application within a Windows or LabVIEW RT environment. By doing so, you decrease the complexity of programming your application, as well as increase the processing power.

Form Factor
Some industrial environments are harsher than others. There might be some areas, such as a production line, where temperature, shock and vibration, and spacing are critical. In those cases, you may benefit from designing your control hardware such that it is close to the system, rather than having wires across the factory floor that can pick up noise or be easily disconnected. National Instruments offers different platforms to implement your industrial and distributed needs, yet if you need signal conditioning, high-speed acquisition and processing, and a small, rugged form factor, CompactRIO is the best platform to meet these requirements.

See Also:
CompactRIO Product Page

Architecture of the Application

When you design an application for CompactRIO, you must first determine how to distribute the code between the different parts of the system—which sections of the code will run in the FPGA, which sections will run in the LabVIEW RT embedded controller, and which sections will run in the host computer. For example, as part of your application you might want to do high-speed data acquisition, advanced PID control, data logging into a file, and web publishing. However, where should data logging be done, in the embedded controller or the host computer? Where is the best place to implement the PID control algorithm, in the embedded controller or the FPGA? The performance of the application could be severely affected if the code is implemented incorrectly.

Let us imagine a standard batch control application, a press-fit system. A press-fit system monitors and controls the force and displacement applied by a mechanical arm to a specific piece of hardware. The objective is that the piece of hardware is compressed based on a certain profile, or force versus displacement curve. This profile is typically defined as a set of "windows," or limits, which create boundaries and trigger conditions for the curve.The system should also include safety features such as a software emergency stop button and proximity sensors to protect human operators from getting injured while operating the machine should exist. As you can see, the batch process involves several areas of consideration with different degrees of importance, which all need to be addressed during the design of the application.

To implement the different parts of a batch process system in CompactRIO, you must develop different software modules that will run in the FPGA, in the embedded controller, and in the host computer. The FPGA in CompactRIO should do the high-speed data acquisition, fixed-point control algorithm, and safety control of the system. The main advantage for implementing these tasks in FPGA is that this code runs hardware-timed and it guarantees that the acquisition of the signals and the control response will be on time. Due to the nature of FPGAs, NI recommends that you implement floating-point operations like PID control or advanced mathematical processing in a floating-point processor system like the host computer or the embedded LabVIEW RT controller.You can implement floating-point operations in an FPGA, however, the FPGA does not natively support them and you would have to implemented manually. In the case of a press-fit system, you should implement the most important and time-critical tasks in the FPGA, like the monitoring of the force and displacement, the validation of each window (pass/fail test), and the monitor of the safety proximity sensors and stop button. You can implement the communication to the FPGA to retrieve valuable information for the process in either the embedded LabVIEW RT application or the host application. There are different ways of communicating to the FPGA, either poll-driven or interrupt-driven. These methods of communication are discussed in more detail later in this document. As mentioned before, floating-point mathematical processing like PID control or signal analysis should be implemented in either the RT or host application. Finally, the user configuration and display interface, as well as other minor tasks like report generation and data logging should be implemented in the host application.

In a batch control process, like a press-fit, the application can be described as follows:

In this diagram, each frame represents an individual loop running in parallel. For instance, the FPGA application could have the custom triggering loop running in parallel with the fixed-point control algorithm. This gives you a full, multithreaded-like application that uses the full power of the FPGA. It is important to notice that in some cases it is not necessary to develop an application that will run in the embedded LabVIEW RT controller. The host application running in a Windows environment can also communicate to the FPGA, read from and write values to it, and implement advanced control techniques.

For most applications, NI recommends the following architecture for an application running on CompactRIO:

CompactRIO FPGA: Data acquisition and highly critical control algorithms should be implemented in the FPGA hardware. All discrete operations can easily be implemented in the FPGA.

LabVIEW RT controller (optional): Use the LabVIEW Real-Time Module to provide reliability and determinism to an application. Communication to the FPGA to send/receive data can be implemented in RT code. Control algorithms that are not as critical for the application, that run at slower rates, or that require floating-point processing should be implemented in RT. Communication to a host application can also be implemented at this level.

Host computer running LabVIEW for Windows: Using TCP/IP, the host VI communicates to the RT VI to synchronize data and update a user interface for display. Data logging should also be implemented for storage of historical information about the application. If LabVIEW RT is not used, all elements of that section can be implemented here.

See Also:
Developing Measurement and Control Applications with the LabVIEW FPGA Module and Reconfigurable I/O Devices

Implementing Hardware-Timed I/O

Developing a hardware-timed application in the LabVIEW FPGA Module is straightforward. After you compile and download a VI to the FPGA, a custom circuit that implements your code is created in hardware. The main advantage of this is that you can have independent loops running completely in parallel. Their execution is truly in parallel, meaning that there is no task scheduling or thread swapping, like in an operating system. All operations within the FPGA execute based on the timing of the 40 MHz clock for the device and not on any element of software. Therefore, develop your application with certain timing requirements in mind and create the LabVIEW application such that it meets these requirements.

For example, a batch process might need a moderate acquisition rate for some analog signals, like force or displacement, but a much higher sampling rate for a stop button. Using the FPGA parallel architecture, the response of the process to a change in an external stop button is not limited by the time it takes to acquire the analog signals.
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In the LabVIEW FPGA Module, use the Timing Functions to control the rate at which your code executes. The Loop Timer function times a loop on a specific interval. This is an effective way of keeping the FPGA code synchronized. The Wait function delays for a certain time interval before the output data dependence becomes valid. Even though the use of Timing Functions gives the impression of a software-controlled loop, like in a Windows or LabVIEW Real-Time platform, the timing constraints are based on the onboard 40 MHz clock, so it is controlled by hardware.
Advantages of Implementing Custom Triggering
Almost all industrial applications that use either analog or digital triggering require only basic functionality. For example, starting the application when a switch is pressed, stopping it after a certain number of cycles have completed, validating that an analog temperature value is within range, or monitoring for an emergency stop condition. What happens, however, when you need more complex functionality? What if you need to start your acquisition when a specific pulse train is received as a digital input? Or what if a combination of analog signals needs to be analyzed and behave in a certain manner before the next part of the application is triggered?

CompactRIO and the LabVIEW FPGA Module offer the perfect platform for implementing any custom triggering for your application. CompactRIO signal conditioning modules offer high sampling rates, which allows you to monitor an analog or digital signal fast enough to verify specific conditions which may trigger your application.

Application Framework for Batch Process
For a hardware-timed batch process, there are two independent triggers that are typically used. For the batch process, there is a discrete trigger or set of triggers that start the process, usually a Start switch or Run button. Then there usually is hardware discrete inputs which can be used to force the process to transition to the next state or stop the process under certain conditions. These inputs may be limit switches or proximity sensors detecting conditions of the process. Lastly, there is always an emergency stop which can halt the batch process. In all cases, these discrete inputs are crucial to the proper functionality of the control application and must be handled accordingly in the FPGA application for CompactRIO.

The architecture for the discrete inputs should appear similar to the follow:

Advanced Analog Triggering
In most high-speed batch processes, the general triggering options are not sufficient. Often there are times when analog feedback signals need to be analyzed to monitor the functionality of the system, and based on this feedback, triggering can occur. As in the press-fit example above, the "Windows" that are used to analyze the force versus displacement curve need to be characterized as custom analog triggers.

The following diagram shows an example of how custom “Window” triggers would be implemented in the FPGA code:

Refer to the document linked below for more details on implementing custom analog triggers using the LabVIEW FGPA Module with CompactRIO applications.

In general, in order to implement a custom trigger for your application, you should define the conditions to which your application needs to respond to the feedback from your system. Determine limits or boundaries for the analog signals and define the actions that should be taken if these limits are exceeded. Identify patterns that could potentially occur and plan for the response of the application if these patterns arise. All of these considerations should be taken in developing the custom analog triggers for your application.

See Also:
Ready Set RIO! Creating Custom Triggering Applications with LabVIEW FPGA

Transferring Data to RT/Host

When Do You Need to Do Datalogging
For feedback to the user interface of the application, all important data from the FPGA code should be transferred, displayed, and logged. For the batch process, the elements that should be transferred are:

• Discrete inputs for start, stop, and limits/proximity
• Analog feedback from the system
• Pass/Fail conditions of custom triggers
• Number of cycles for the batch (units tested)

There are two approaches you can take to transfer data from FPGA to RT or Windows. First, you can use an interrupt-driven architecture to transfer data in a handshaking fashion.

The advantage of using the interrupt-driven architecture is that it only transfers data when an interrupt is generated, thus alleviating CPU usage on the RT or Windows system. As a disadvantage, the loop rates that are achievable and sustainable are good, but may not be fast enough for some applications and could be increased by using a polling method.

A polling method can be used to continuously read the data that is available from FPGA. In contrast, although polling provides faster transfer rates, you must work with the caveat that you could potentially read duplicate data in your polling loop. With the interrupt-driven architecture, handshaking prevents this from happening. You must use a method for notifying the polling loop that new data is available must be used to prevent duplicate data from actually being processed.

If your batch process loop executes at a hardware-timed rate of approximately 3 KHz or less, using an interrupt-driven architecture is the best option. If your application needs higher loops rates, use the polling method to maintain adequate data transfer.


Utilizing FPGA FIFOs
For either case, it may be advantageous to use FPGA FIFOs to ensure that no data is lost while maintaining a hardware-timed loop. The application should be designed such that your hardware-timed acquisition can run continuously without being interrupted. It is also crucial that all discrete inputs are read and processed instantaneously, as they may have a big impact on the batch process.

Without interrupting these loops, data still needs to be transferred to RT or Windows for display and logging. Use FPGA FIFOs to buffer the data for transfer and ensure that no data is lost.

Refer to the LabVIEW FPGA Module User Manual, available by selecting Start»Programs»National Instruments»LabVIEW 7.1»Module Documents, and the VI, Function, & How-To Help in LabVIEW for more information on using FPGA FIFOs to transfer data between parallel loops.

Using Fixed-Point and Floating-Point Control

As we have discussed in the triggering section, there are two sets of I/O that are used in a batch process: digital and analog. Digital I/O includes the inputs to the system to start and control the batch process and feedback from the system on the progress of the batch. Analog I/O is used to control the hardware used in the batch process, such as the press-fit arm, and as feedback of characteristics of the system such as force or displacement.

In order to develop an application that properly operates the system, you must use control techniques. The level of complexity of the control needed varies from application to application, but understanding how to implement control using LabVIEW with CompactRIO is important in developing an optimized application.

Implementing Fixed– or Floating–Point Control

Fixed-Point
For all Digital I/O, you should implement control in the FPGA. Because FPGA is built with gates and Boolean logic, it is perfectly suited for fixed-point control techniques. For the batch process, this would involve analyzing all inputs which relate to the progress of the process or inputs that may have a bearing on how the software responds to the system. For example, in the press-fit application, the limits switches, proximity sensors, pass/fail conditions of customs triggers, and emergency stops all factor into the software control of the application. Based on the results of the control logic from the inputs, outputs can be generated accordingly.

For most fixed-point control, you can use standard LabVIEW programming techniques, such as the Boolean functions and case structures. If you need more advanced control techniques, functions in FPGA are available to assist in the implementation.

For more information on using control functions in FPGA refer to the LabVIEW FPGA Module User Manual and the VI, Function, & How-To Help in LabVIEW.


Floating-Point
Based on the feedback from the system, you may need to implement control to operate the hardware in the system, such as the press arm in a press-fit system. In this case, control techniques that require floating-point numbers may be needed. If so, all floating point operations should be performed in the RT or Windows portion of the application.

For floating-point control, the most common type of control used is PID. When implementing PID control for the analog I/O in your system, be aware that all analog data is represented in integer format and must be scaled to a floating-point number before applying the control algorithm to ensure proper analysis.


A wide variety of documents about floating-point control techniques are available on the National Instruments Web site. Go to www.ni.com/support for more information. You can also use the PID (Host) VI example, available in the NI Example Finder by selecting Toolkits and Modules» FPGA» Fundamentals» Analysis» Control» PID (Host) VI, for a more detailed illustration of implementing PID for FPGA.

See Also:
National Instruments Support

Summary

For all hardware-timed batch processes, follow the general objectives listed below to successfully develop a CompactRIO system that meets your application's needs.

1. Requirements of System—Determine the I/O that is needed for your system and define the requirements for speed and control.
2. Selecting CompactRIO—Based on the speed, size, and I/O requirements, select the appropriate form factor for CompactRIO and the most suitable signal-conditioning modules.
3. Application Framework—Utilize the general architecture for the discrete inputs of your system for starting, monitoring feedback from limit switches or proximity sensors, and processing stops.
4. Implementing Hardware-Time Acquisition: Utilize the timing functions of FPGA to guarantee determinism.
5. Custom Triggers—Define specific hardware input conditions used to drive the application.
6. Data Transfer—Use interrupt-driven transfer for batch processes running at approximately 3 kHz or less.
7. FPGA FIFOs—Utilize FPGA FIFOs to protect all important data while not interrupting critical tasks in the FPGA code.
8. Implementing Control—Implement fixed-point, discrete control in FPGA and floating-point control in RT or Windows.

In sum, all systems will contain different requirements and the hardware and software needs to be able to adjust to these changes. CompactRIO and LabVIEW provide a flexible and rugged hardware and software solution to suit the needs of most batch process applications.

See Also:
CompactRIO Product Page

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