Developing High Speed Continuous Buffered Data Acquisition Applications with CompactRIO

When developing high speed data acquisition applications using LabVIEW FPGA, there are a number of built-in functions that allow you to buffer the data in the FPGA memory space and transfer it to a real-time or Windows host processor without loss. Click here to download the buffered data acquisition LabVIEW example program described in this application note. This example performs continuous buffered waveform acquisition. A typical buffered data acquisition application typically consists of the following components:

Reconfigurable FPGA Application
· Read measurement values from CompactRIO I/O modules at programmable scan rate
· Write values to FPGA FIFO for buffering in FPGA memory
· Read values from FPGA FIFO and place values in front panel indicator for transfer to host processor

Real-Time or Windows Host Processor Application
· Read Scan Backlog value to determine the number of samples available in the FPGA FIFO
· Read measurement values from FPGA front panel indicator
· Use Calibration values to scale the measurement values to voltage or other engineering units

Developing the Reconfigurable FPGA Application

In this reconfigurable FPGA application for buffered data acquisition, 4-analog input channels are simultaneously sampled by the cRIO-9215 module in the Acquisition and Buffering loop. A Loop Timer function with 1 microsecond resolution is used to determine the sampling rate for the analog input module. The LabVIEW FPGA compiler will always start functions simultaneously and execute them in parallel if no data dependency or programming structure exists to define the timing relationship of the functions. The sequence structure placed around the Loop Timer and Analog Input functions ensures correct timing on the first several iterations by guaranteeing that the Analog Input operation occurs after the Loop Timer delay (rather than executing the functions simultaneously).


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Once a scan of data has been acquired, it is assembled into an array using the Build Array function and passed to the FIFO Write function. In this case, the FIFO Write function is configured to use a memory block consisting of 12,000 16-bit signed integers (I16’s). By placing the FIFO Write function in a While Loop with the conditional terminal wired to the FIFO Full signal and set to Continue If True, we ensure that the FIFO Write function will continue attempts to write the data into the FIFO if it is full. In this way, we can insure that data is never overwritten in the FIFO. This will cause the acquisition to slow down if the FIFO is full until the host application reads more data and space becomes available in the FIFO. The same result could have been obtained by removing the While Loop and setting the Timeout input on the FIFO to -1, which would cause the FIFO to wait indefinitely for space to become available it were full. However, by setting the Timeout to 0 and placing the FIFO Write function in a While Loop we are able to monitor the status of the FIFO using the FIFO Full indicator.

The Communication to Host loop sends the measurement data to the host processor by reading the values from the FIFO using the FIFO Read function and passing it to the Input Data (Synchronous Display) indicator. The For Loop around the FIFO Read function has Autoindexing enabled on its output terminal to rebuild an array containing one scan of analog input data. The Synchronous Display option on the indicator provides handshaking with the host processor by preventing subsequent values from being written to the indicator until the previous value has been read by the host. To enable the Synchronous Display option in LabVIEW 7.1, navigate to the front panel of the FPGA application and right-click on the indicator, then navigate to Advanced and select Synchronous Display.

The Scan Backlog variable is used to indicate the number of scans of analog input data available in the FIFO. The iteration terminal on each loop is a signed 32-bit integer (I32) that starts at zero and increments by one on each execution of the While Loops. The signed iteration values are converted to unsigned 32-bit integers (I32’s) in order to avoid incorrect readings when the iteration terminals reach their maximum value and roll-over. By using unsigned integers, the Scan Backlog value will be correct even when the Comm ID and Scan ID values roll-over. In general, unsigned integers should be used rather than signed integers when performing math operations on counter values.

When using the CompactRIO Reconfigurable Embedded System, the data transfer rate between the RIO FPGA chipset and the embedded CompactRIO real-time controller is typically limited to about 70-100 kB/s. If the data is transferred as 16-bit words, this is equivalent to transferring the data from a 35-50 kS/s acquisition from one channel. The specific maximum transfer rate depends on the amount of processing and other operations that are performed in the LabVIEW Real-Time application. Using a PXI-8176 controller booted into the LabVIEW Real-Time operating system, the data transfer rate from FPGA to real-time controller is typically limited to about 500 kB/s. If the data is transferred as 16-bit words, this is equivalent to transferring the data from a 250 kS/s acquisition from one channel.

During LabVIEW FPGA application development, you can read the calibration coefficients that are stored on the module EPROM by using I/O Property Nodes. These coefficients are programmed at the factory using a NIST-traceable calibration procedure. In addition to the calibration data, the I/O Property Nodes can also be used to read other data stored on the module EPROM, such as the module type and module serial number.

As a best programming practice, the I/O Property Nodes should be executed only on the first call of the FPGA application or when requested by the host application, so they cannot interfere with the timing of analog input operations.

In the example shown below, the calibration data is read from each channel of the cRIO-9215 analog input module and assembled into a calibration cluster. After reading the calibration coefficients from the module in the LabVIEW FPGA application, Bundle function are used to create a calibration cluster that will be read by the Real-Time or Windows host application and used to scale the data to calibrated voltage values.

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Developing the Real-Time or Windows Host Processor Application

A typical real-time or Windows host processor application for high speed buffered data acquisition application typically reads the calibration data from the FPGA, reads the Scan Backlog to determine the number of samples available in the FPGA FIFO, reads that number of scans of measurement data from the FPGA, and then scales the measurements to voltage or other engineering units using the calibration data.

In the example shown below, a cRIO-9004 controller running LabVIEW Real-time reads the calibration cluster from the FPGA. The While loop around the Read/Write Control for the calibration data guarantees that the host application will not continue until valid calibration data is read by the FPGA.

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The real-time host processor application then reads the Scan Backlog from the FPGA and uses the Scan Backlog to determine how many scans of data to read from the FPGA. In this way, the application can guarantee that it will not read the same scan more than once. Because the Communication to Host loop in the FPGA application is so much faster than the host processor, new data will always be available in the Input Data (Synchronous Display) indicator whenever the Scan Backlog is greater than 0.

To perform scaling on the host application, there are support files for each CompactRIO I/O module located in the Examples folder of your LabVIEW installation. These support files use the calibration cluster provided by the FPGA application to perform scaling to floating-point voltage units. In this case, the Convert to Voltage (cRIO-9215).vi support file is used to scale the analog input data to Voltage units.

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Click here to download the example program

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