Introduction to NI R Series Intelligent DAQ

NI R Series intelligent data acquisition (DAQ) devices incorporate field-programmable gate array (FPGA) technology to deliver a customizable hardware solution for measurement and control systems. Using the NI LabVIEW FPGA Module, you can create custom hardware functionality by programming LabVIEW block diagrams that run directly on the FPGA. You can address a wide variety of applications requiring precise timing and control using this system based on LabVIEW.

Introduction to FPGA Technology

Using R Series intelligent data acquisition (DAQ) devices, you can easily create user-defined hardware configurations for measurement and control applications. Previously, this sort of solution was possible only with custom-designed hardware; however, with field-programmable gate array (FPGA) technology, R Series provides an off-the-shelf solution.

An FPGA chip consists of unconfigured logic gates and programmable interconnects. Unlike the fixed, vendor-defined functionality of an application-specific integrated circuit (ASIC) chip, you can reconfigure an FPGA for each specific application. They are often used in applications where the cost of developing and fabricating an ASIC is prohibitive, or where the hardware must be reconfigured after being placed into service. Because algorithms implemented on the FPGA run with determinism in hardware, they offer benefits such as precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks.

Today, FPGAs appear in many different devices such as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific computer hardware. While they are often incorporated in products for measurement and control, users of these products are generally hesitant to develop their own FPGA-based systems. Configuring an FPGA typically requires expertise in board-level hardware description languages (HDLs) such as VHDL and Verilog, which are generally used more by hardware design engineers than by test and control engineers.

Now, using the NI LabVIEW FPGA Module, you can create these FPGA-based measurement and control applications in a higher-level graphical development environment. No other complex design tool knowledge is required. You can configure hardware functionality by placing blocks on the LabVIEW block diagram and you can compile them down to a bit stream containing information on how the FPGA reconfigurable logic blocks should function and be wired together.

To learn more about the power and flexibility of FPGA technology, visit the FPGA Technology resource page.

Common R Series Applications

R Series intelligent DAQ devices provide an off-the-shelf solution for a wide variety of applications needing custom hardware functionality.

High-Speed Analog and Discrete Control

Advanced control systems require determinism, speed, and reliability. FPGA-enabled R Series intelligent DAQ devices offer a platform for developing such systems. They are able to scan and set multiple digital lines while making control decisions in a fraction of a microsecond. The possibility of unanticipated latency is eliminated because the VI executes with hardware determinism on the FPGA rather than in software where there is operating system overhead. Additionally, new Virtex-5 R Series devices sample 16-bit data at up to 750 kHz, and analog output channels update as fast as 1 MHz. You can even execute many control algorithms in a single cycle of the FPGA clock (40 MHz) to implement high-speed decision making at extremely fast loop rates. Rather than scheduling tasks and sharing resources, like in processor-based systems, FPGAs operate with true parallel execution and have dedicated hardware resources for each task. This ensures maximum performance and reliability because applications do not slow down when you add more processing. The LabVIEW FPGA Module makes it easy to implement common control algorithms, such as proportional integral derivative (PID), as well as custom algorithms.

View case studies on high-speed analog and discrete control:
- CERN Uses LabVIEW FPGA and Intelligent DAQ to Control World’s Largest Particle Accelerator
- High-Speed Laser and Motion Control with Intelligent DAQ
- OptiMedica Uses R Series Intelligent DAQ to Improve Retinal Disease Treatment

Digital Protocol Emulation

Many applications require that systems interface to devices using uncommon or custom digital protocols. Often, hardware for this is either not available or not affordable. The onboard FPGA in R Series intelligent DAQ devices can perform high-speed digital processing to decode and encode messages with a high degree of flexibility. As a result, R Series intelligent DAQ devices serve as a flexible interface module for virtually any communications protocol.

View case studies on digital protocol emulation:
- Automated High-Voltage Defibrillator Testing Using Multiple Digital Communications Protocols
- Using R Series Intelligent Data Acquisition for Bit-Error-Rate Test

Protocol Aware Test

For some test environments, such as semiconductor validation, previous test methods using standard digital test vectors have become more difficult due to the increasing complexity of chips. This complexity has led to the demand for "protocol aware" automated test environments, where testers emulate real-world signals around the chip. Rather than generating a list of expected patterns, the tester intelligently sends and receives commands, quickly makes decisions, and emulates digital communications protocols. R Series intelligent DAQ devices work well for these applications because the onboard FPGA can perform the high-speed processing required to make intelligent decisions and properly emulate digital protocols.

Custom Measurements

R Series intelligent DAQ devices offer a new level of timing control and synchronization capabilities to measurement system development. Typical data acquisition devices have fixed timing, triggering, and synchronization options built into high-level driver VIs, such as NI-DAQmx, that can address the majority of data acquisition applications. Some applications, however, may have specific requirements that these fixed functions cannot meet. Using an R Series intelligent DAQ device, all timing, triggering, and synchronization functionality is defined by LabVIEW block diagrams that run in hardware. You can implement specialized functionality such as independent channel triggering, multirate sampling, and high-speed onboard decision making. In addition to this custom timing and triggering functionality, R Series intelligent DAQ devices have been useful in applications requiring flexible encoder interfaces, pulse-width modulation (PWM) communication, and custom counters.

Flexible Encoder Interface

An encoder is a device used for measuring speed or position. As a shaft rotates, pulses are generated indicating degrees of rotation. There are many different types of encoders available, and some applications may use several different types together. Using the LabVIEW FPGA Module, you can configure R Series intelligent DAQ devices to interface to multiple types of encoders on separate digital lines and reconfigure them for different applications. You can even implement custom functionality such as reading the encoders synchronously with other signals.

View R Series tutorials on implementing encoders:
- Quadrature Encoder Example DAQ Personality

PWM Communication

PWM signals are common in many industries, such as automotive and telecommunications. In a PWM pulse train, the frequency is held constant, and the information is conveyed by the duty cycle — the percentage of time the pulse is high. Many typical data acquisition devices do not adequately handle rapidly changing duty cycles or allocate a fixed number of channels for static PWM. With the LabVIEW FPGA Module, you can configure any of the digital lines on an R Series intelligent DAQ device to read or write PWM signals and easily handle moving duty cycles.

View R Series tutorials on implementing PWM communication:
- Pulse-Width Modulation Example DAQ Personality

Custom Counters

Typical multifunction data acquisition devices come with two general-purpose counters. R Series devices have up 160 digital I/O lines in which you can implement counters. Using the LabVIEW FPGA Module, you can create custom counters to achieve synchronization, implement custom counting options, or meet any specific application need.

View R Series tutorials on implementing counters:
- 64-Bit Counter Example DAQ Personality

Sensor Simulation

Sensor simulation is the process of providing realistic sensor signals to the inputs of a device under test (DUT) and evaluating how a piece of equipment responds across a broad range of operating conditions. The greatest benefit to simulating sensors is the ability to push past the operational limits of a specific environment and test fault conditions that would otherwise be damaging or dangerous. You can implement changes to system components without fear of destroying expensive equipment. These simulated signals can range from simple analog waveforms to custom digital protocols. The onboard FPGA in R Series intelligent DAQ devices has the flexibility and inherent parallel processing capability to simultaneously simulate a variety of sensors in real time. Rapid control prototyping and hardware-in-the-loop (HIL) simulation are two common methods of sensor simulation.

Rapid Control Prototyping (RCP)

Electronic controllers are often used in many products such as vehicles and household appliances. In the early stages of development, before the controller is built, the control algorithms must be tested with the system to be controlled, or the plant. To accomplish this, the RCP system simulates the functionality of the controller. It is connected to the actual hardware actuators and hardware sensors of the plant, where it uses specifically designed algorithms to test the system. R Series intelligent DAQ devices are used to simulate these controller signals and perform high-speed processing on measured signals.

View case studies on rapid control prototyping:
- Development of an R Series Rapid Control Prototyping Platform for Advanced Engine Control Systems

Hardware-in-the-Loop (HIL) Simulation Testing

In addition to RCP, R Series devices are useful in applications requiring HIL simulation testing of electronic controllers under development. In these applications, rather than simulating the controller, a real controller is used and the plant is simulated. For example, if an engine control unit (ECU) for a car is being tested, simulating gives the ability to test the ECU without having to build the car multiple times. HIL configurations are also useful for testing controllers under extreme conditions that could not be replicated conveniently in a laboratory. R Series devices are used in these systems to simulate sensor outputs, generate and decode PWM signals, and perform onboard decision making based on measured values. With this type of architecture, the need for multiprocessor systems, which are often used to handle both the simulation and I/O in many systems today, is eliminated.

View case studies on HIL simulation testing:
- MicroNova Uses LabVIEW FPGA and Intelligent DAQ for Exact and Comprehensive Engine Simulation

R Series Intelligent DAQ Devices

National Instruments offers a variety of FPGA-enabled R Series intelligent DAQ devices that vary depending on sampling rate, I/O, form factor, and FPGA size. New Virtex-5 R Series devices offer higher performance, faster I/O, and larger FPGAs.

Table 1. R Series Intelligent Data Acquisition and Control Devices

R Series intelligent DAQ devices are based on a Xilinx FPGA core that is surrounded by fixed analog and/or digital I/O. Figure 1 shows an NI PXI-7854R multifunction R Series intelligent DAQ module. The onboard Virtex-5 FPGA handles the timing, synchronization, and decision making. It also interfaces to the analog I/O, digital I/O, and the Real-Time System Integration (RTSI) bus, which is used to easily synchronize several measurement functions to a common trigger or timing event. R Series PXI modules access the RTSI bus through the PXI trigger lines implemented on the PXI backplane, while PCI boards access the RTSI bus through a RTSI cable connected between devices.

Multifunction R Series devices feature a dedicated 16-bit analog-to-digital converter (ADC) per channel for independent timing and triggering and sampling rates up to 750 kS/s. This provides specialized functionality such as multirate sampling and individual channel triggering, which are outside the capabilities of typical data acquisition hardware. Multifunction R Series devices also include a 16-bit digital-to-analog converter (DAC) for analog output update rates up to 1 MS/s and up to 96 digital I/O lines. Onboard flash memory is used to configure modules and store a startup VI for automatic loading of the FPGA when the system is powered on.

Typical Multifunction I/O DAQ versus Intelligent DAQ

There are many key differences between typical NI data acquisition modules (for example, NI M Series, E Series) and R Series intelligent DAQ modules. The NI-DAQmx driver delivers a high-performance, intuitive API with predefined counter/timer, triggering, and acquisition functions that can meet 90 percent of data acquisition application challenges. However, some applications may require custom functionality not directly featured in the NI-DAQmx driver. R Series intelligent DAQ devices help fill this gap because you have low-level hardware control of the I/O and can perform high-speed, single-point analog input and output. You can implement custom timing, triggering, and I/O synchronization on the FPGA to meet these custom functionality requirements. Table 2 shows a comparison of a typical DAQ device and an R Series intelligent DAQ device.

You configure the functionality of an R Series intelligent DAQ device by programming the FPGA using the LabVIEW FPGA Module. Because you implement the LabVIEW block diagram in hardware, you have direct control over the I/O. You can analyze each I/O signal and manipulate them in ways that are not possible with fixed I/O hardware. On a typical DAQ device, you implement counter logic in a fixed ASIC chip such as the DAQ-STC and program the application using NI-DAQmx Counter VIs. However, using an R Series intelligent DAQ device, you implement the counter on the FPGA using the LabVIEW FPGA Module. Figure 2 shows the block diagram for a simple 16-bit rising-edge counter from a LabVIEW FPGA example program. Normally, this implementation in LabVIEW for Windows can count only very low-frequency edges because there is no hardware determinism. However, because the LabVIEW FPGA Module actually implements the block diagram in hardware, it can use a derived 80 MHz timebase and have similar performance to defined counters on a typical data acquisition device.

Figure 2. Sample LabVIEW FPGA Program – 16-Bit Counter

NI ships the LabVIEW FPGA Module with LabVIEW VI examples for a variety of common functions, which you can modify to meet custom application requirements. Some topics covered in the examples include the following:

• PWM
• Timed, synchronized operations
• Custom counter and encoder interface
• Custom triggering methods
• DMA transfer
• Signal processing

In addition to the built-in LabVIEW functions, the LabVIEW FPGA Module features more than 100 intellectual property (IP) blocks, including math, signal processing, control, and communications, to jump-start application development. Visit IPNet - LabVIEW FPGA Functions and Example IP to get started.

Intelligent DAQ Application Development

Programming with the LabVIEW FPGA Module is similar to programming LabVIEW for Windows. You use the same basic program constructs (for example, while loops, for loops, cases, and sequence structures). You need to create one VI to run on the FPGA to implement any logic for signal synchronization, custom digital protocol communication, PWM communication, or onboard decision making. You can create a second VI to run on the host computer to handle communication and data transfer between the FPGA and the host. If you do not need any user interface or host processing, you don't need the host VI.

Developing the FPGA VI

Figure 3 shows a simple LabVIEW FPGA PID control algorithm. The FPGA I/O Node takes a single sample from analog input channel AI0. The value is passed to the PID VI, which performs the PID calculation and then outputs the result to a second FPGA I/O Node, which writes the value to analog output channel AO0. The loop timer defines how long the device waits before moving on to the next iteration of the loop, where the next sample is taken and the next PID calculation is made.

Figure 3. LabVIEW FPGA VI - Basic PID Control

You can use the FPGA device emulator to help debug the FPGA VI before it is compiled for the FPGA. When emulating, all logic is executed on the host computer processor and the emulator uses either simulated I/O or the actual I/O on the R Series device. Although you cannot achieve hardware determinism, the emulator provides the ability to test and debug the FPGA VI before it is compiled. You can use all of the typical LabVIEW debugging tools such as highlight execution, probes, breakpoints, and single stepping, which are not available after compilation.

Just as with other FPGA development tools, the compile step can take minutes to hours depending on application complexity and computer resources. If the FPGA VI needs to be tested with the speed and determinism of hardware performance, it must be compiled rather than run with the FPGA device emulator. You can start the compile by first targeting the R Series intelligent DAQ device rather than the FPGA device emulator and then simply clicking the Run button. Because the VI targeted to the R Series intelligent DAQ device runs in hardware without the overhead of an operating system, execution is completely deterministic.

Developing the Host VI

You can use the host VI to communicate between the R Series intelligent DAQ device and the host computer. A host computer is useful for performing floating-point calculations, data logging, networking, and any calculations that do not fit on the FPGA. Figure 4 shows the host VI for the PID control example shown in Figure 3. In this example, the host VI simply monitors and sets control values for the FPGA VI. The first step in building a host VI is to open a reference to the FPGA VI and R Series intelligent DAQ device, which downloads and runs the compiled FPGA code during execution. After opening the reference, the control and indicator registers can then be read and written to on the FPGA using the Read/Write Control function. In this example, the Read/Write Control function sets the loop rate and continually reads and writes the values from the controls and indicators of the FPGA PID VI. The Invoke Method function is used to initially run the VI.

Figure 4. LabVIEW Host VI - Analog Input

You have several additional ways to control data transfers between the R Series intelligent DAQ device and the host computer. For single-point data transfers, you can synchronously transfer data by generating a physical interrupt from the FPGA to signal data transfer with the host. For large data transfers, LabVIEW FPGA includes three DMA channels that you can use for streaming data from the R Series intelligent DAQ device.

Performance Benefits

The ability to run LabVIEW block diagrams with hardware determinism on the FPGA of R Series intelligent DAQ devices offers performance that is typically much better than that of software-based systems. For example, consider an application with eight PID control loops. Using a real-time target to perform the eight PID calculations and using the R Series intelligent DAQ device only for I/O, you can achieve a 28 kHz loop rate. On the other hand, by implementing an integer-based PID algorithm on the FPGA of the R Series intelligent DAQ device (shown in Figure 5), you can achieve a rate of 100 kHz for each of the eight loops.

Figure 5. Eight Parallel PID Calculations Performing at a Rate of 100 kHz per Loop

This performance improvement is due to the true simultaneous, parallel processing capability of NI R Series intelligent DAQ devices. Processing on a host computer requires the division of CPU time between several tasks. However, implementing multiple parallel while loops on a LabVIEW FPGA block diagram actually creates multiple hardware processes on the FPGA that operate simultaneously but can be synchronized to the global clock.

Conclusion

With powerful, new FPGA technology, R Series intelligent DAQ devices can serve a variety of measurement and control applications. With their reconfigurable functionality, you can create custom, high-performance measurement and control systems that were previously difficult to address or required custom hardware design. The LabVIEW FPGA Module streamlines the process of configuring FPGAs and provides a flexible off-the-shelf data acquisition solution.

Learn More about NI R Series Intelligent DAQ Devices

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