Digital Measurements: Logic Families, Digital Level and Drive States

This tutorial is part of the National Instruments Measurement Fundamentals series. Each tutorial in this series, will teach you a specific topic of common measurement applications, by explaining the theory and giving practical examples. This tutorial covers the voltage levels of digital signals.

You can also view an interactive presentation that takes you through this tutorial's material at your own pace.

For information about the timing of digital signals, refer to the Digital Waveform Timing tutorial.

For the complete list of tutorials, return to the NI Measurement Fundamentals Main page

Single-Ended and Differential Digital Signals

Digital signals can generally be classified into two categories: single-ended signals and differential signals. The details of each of these two types of signals and their measurement fundamentals are given in the following section.

Single-ended digital signals:
When most engineers think of digital signals, they think of single-ended digital signals. In single-ended signals, a digital transmitter drives out one voltage (called V_OL or Voltage Output Low) to represent a logic level '0' and another voltage (called V_OH or Voltage Output High) to represent a logic level '1'(please refer to Figure 1). Both of the V_OH and V_OL voltages are referenced to ground. For more common single-ended logic families like TTL or CMOS, V_OL is equal to ground. V_OH is commonly 3.3V or 5V, although there is a push in the industry to continue to lower V_OH in order to achieve lower power and faster digital designs.

At the single-ended digital receiver any voltage less than one voltage (called V_IL or Voltage Input Low) is interpreted to represent a logic level '0', and any voltage greater than a voltage (called V_IH or Voltage Input High) is interpreted to represent a logic level '1'. The difference between V_OH and V_IH and the difference between V_OL and V_IL are known as the Noise Immunity Margins (NIM) and determine how much noise can be on the digital signal before the receiver cannot correctly receive the digital signal.

Differential digital signals:
While most digital signals today are still single-ended, there is a growing number of differential digital signals in use today. LVDS, ECL, PECL and RS-422 are some of the most common of the differential digital signals. Differential signals have one distinct advantage; they are immune to most types of signal noise. Instead of 1 wire and a ground to transmit digital signals, differential signals take 2 wires configured as 1 pair. Since the differential signal uses two wires to transmit a signal, most noise that gets added to the lines will be of the same magnitude to the two wires and hence essentially the voltage difference between them still remains to be as intended. The digital driver still drives out two voltages, V_OH and V_OL as in the single-ended case.

[+] Enlarge Image
Figure 1. Types of digital signals

The receiver, however, interprets the signals based on the voltage difference between the pair of signal - not based on a reference to ground. For the differential digital signal to be received as a logical '0', the V+ signal must be less than the V- signal by more than V_diff. This V_diff is specified by the particular voltage standard. For example, the V_diff for LVDS is 100mV. While differential signals are not specifically referenced to ground like single-ended signals, they are generally limited in the range of valid voltages. This is usually specific in terms of the midpoint or average of the two voltage levels and is called the common mode voltage (VCM).



View Interactive Presentation

Logic Families

Table 1 shows that many of the commonly used digital voltage standards are covered in the range of -2 to 5.5 V range. It includes single-ended standards as TTL, LVTTL, CMOS, and also differential standards like ECL and PECL.

Table 1. Logic family voltage standards

Please follow the links below for more detailed information on NI's High-Speed Digital Devices measurement capabilities:

• Interfacing NI PXI-655x Digital Waveform Generator/Analyzers to ECL/PECL Logic Families
• Interfacing to LVDS with the NI 655X Digital Waveform Generator/Analyzer
  
  View Interactive Presentation
  
  

Digital Drive States

We have already discussed that in digital systems, there are two logical states: 0 and 1. While for most digital systems this is true, there are actually more logical states than 0 and 1 - especially in the digital test market.

Another logic state is 'Z' also referred to as "tri-state." This is the state where the driver is not driving any value at all (please refer to Figure 2). To be clear, it is not equal to either 0 or 1. Physically the potential of the wire is floating at an unknown voltage level.

[+] Enlarge Image
Figure 2. Digital drive states

The most common use of the Z state is when it is used to test one or more digital lines that can be driven by multiple transmitters. The data port on a memory chip is a good example of this. When the computer writes into the memory device, the computer needs to drive the data to be written into the memory chip on the data pins of the memory device. Later, when the computer processor needs to read out the contents of the memory, the memory device needs to drive the previously stored data value back to the computer processor.

Another logic state is 'X'. X can mean different things depending on whether the device is a transmitter or a receiver. From the transmitter perspective, the X value means "whatever logical value you were previously transmitting - keep transmitting it." This can be used in an application where at the start of the application - the user does not know what logic levels the transmitter was previously left in, but they need to continue in that state.

For digital receivers, X means "don't care". This is most commonly used when, in a user application, you are comparing the Device Under Test's (DUT) actual, captured response to some theoretical value. You may know for instance that you are expecting the DUT to produce the pattern 0 1 0 0 1 0 1. But many times, the DUT may produce more samples that you actually care about. For example, if a PASS condition is defined as 0 1 to start the pattern followed by three samples of data that may change from time to time, followed by a trailing 0 1 - then you can use the don't compare to compare the 0 1 0 0 1 0 1 against 0 1 X X X 0 1.

In the digital test world, there are actually many more logic levels than the four mentioned above, however they are much less common and hence not discussed here.



View Interactive Presentation

Voltage Measurements with a Digital Device

Before starting the further discussion about a digital tester, let's take a look at what the front-end of a typical digital tester looks like.
In Figure 3, you can see one channel of the digital test device on the left. It is connected via a wire to 1 device under test (DUT) on the right. The first thing to notice is the variable voltage pin electronics driver in the upper left hand corner. This driver is used when the digital test device is used to transmit digital signals. This pin driver is designed to be able to drive a wide range of V_OH and V_OL voltages for producing digital signals. When the digital test device drives a logic '0', this pin driver drives the Generation Voltage Low (V_OL) voltage out to the DUT. When the digital test device drives a logic '1', this pin driver drives the Generation Voltage High (V_OH) voltage out to the DUT. The pin driver is also capable of "driving" the "Z" state - that is, turning itself off.

The next thing to notice is that there is an effective 50 Ω series resistance at the output of this driver. The known value of this resistance has two purposes. The first is to maximize signal integrity. The second is to aid in measurements of current flows.

In the bottom left of the diagram, two separate comparators can be seen. A comparator is a device that compares the voltage on the DUT pin to a known voltage. For the digital tester, one comparator compares the DUT voltage to V_IL (Acquisition Voltage Low) and a separate comparator compares against V_IH (Acquisition Voltage High). Using these two comparators and the Data Interpretation logic shown in Figure 3, a digital tester can not only determine a valid '0' and a valid '1' but can also determine if the DUT is driving an invalid voltage between V_IL and V_IH.

Figure 3. Digital test front-end architecture

The last circuit element on the diagram is the 10 kΩ resistor connected to ground. The purpose of this resistor is simply to provide a known input impedance to the digital test device.

One more very important thing to note is that the ability of the digital tester to measure the DUT pin with its dual comparators is completely separate for the digital tester's ability to drive voltages to the DUT. This separation of drive and measure capabilities is a very important part of the digital tester architecture.

Digital Tester vs Analog Measurement Devices:
Traditionally, we all think of making voltage measurements with an analog measurement device. What types of devices could be used to measure the V_OH and V_OL of a DUT?

Common and correct answers include a Digital Multimeter (DMM) or a Data Acquisition (DAQ) device. The benefits of using devices like these are that they are well understood and generally they are very simple to use. The devices use their analog to digital converters (ADCs) to easily make single or multiple voltage measurements. They are also very accurate with microvolts or even nanovolts of accuracy. But there are also some drawbacks of using these devices. DMMs usually have a single channel and must employ a switching solution to measure the voltages on multiple digital pins. DAQ devices have more channels than a DMM - but generally, in systems where the digital tester is connected to the digital DUT pin for the majority of the tests, even the DAQ channels must be switched onto the DUT pin to make this measurement.

So the next question is "Can we use the digital tester that is already connected to our DUT to perform the same measurement?" The answer is "Yes." The benefits are that usually the digital test device is already connected to the DUT, and with the large number of channels in most digital testers you can test a large number of channels in parallel. Also, the measurements are not very complex to make. One drawback of using the digital tester is that it is generally less accurate and you can only expect accuracies of about 10mV.

View Interactive Presentation

Shorts / Opens / Stuck-at Fault Tests

In both functional and process testing in manufacturing, there are three very common types of process faults that need to be detected for digital circuits. These are shorts, opens, and stuck-at faults. Let's take a look at these faults and how to test for their existence.

The first fault type is a short. Simply, a short can be defined as an unintended connection between two signals. This can be commonly caused by an excessive amount of solder on a pin that causes it to connect to an adjacent pin.

Figure 4. Shorts / Opens / Stuck-at faults

The second fault type is an open. An open is the lack of a connection between two signals that are supposed to be connected. This can be caused when the pin of a device is not soldered correctly to a pad on the PCB. As shown in Figure 4, it can also be caused if the manufacturing process causes an etching away of a required circuit element.

The third fault type is a stuck-at fault. They are called stuck-at faults because the digital signal is essentially stuck at a particular voltage. General a circuit element is stuck-at-0 or stuck-at-1. One common cause of a stuck-at fault is a short to one of the two power rails of the DUT. But there are many other reasons that can cause a fault like this.

The following discussion covers the testing for shorts and stuck-at faults since the general techniques are very similar. First we need to see what a "Marching 1" or a "Marching "0" pattern is. The general idea is that in order to perform this test, we want the digital tester to be able to isolate each pin from the others on the DUT and test that pin in isolation. The marching patterns are one technique to do this.

Consider the following sequence of digits:

As we can see, it is called a marching 1's pattern because there is a single logical 1 that looks like it is marching to the right. The idea of the single logical 1 - one per pattern, is that the pin being driven with the logical 1 is the signal we are isolating for that test. The digital tester can detect short and stuck-at errors by first writing each marching 1's pattern to the DUT and then reading that pattern back. Faults will appear as differences between what the digital tester wrote to the DUT and what it read back.

Guidelines to do testing for shorts and stuck-at faults are as follows:

Figure 5 (a). PassTest


Figure 5 (b). Short Test


Figure 5 (c). Stuck-at Test

View Interactive Presentation

Relevant NI Products

Customers interested in this topic were also interested in the following NI products:

• LabVIEW Graphical Programming Environment
• SignalExpress Interactive Software Environment
• High-Speed Digital I/O
• Digital Multimeter (DMM)
• Data Acquisition (DAQ)
• Switching

For the complete list of tutorials, return to the NI Measurement Fundamentals Main page.

43 ratings | 4.09 out of 5

Read in English German Japanese | Print | PDF

Reader Comments | Submit a comment »

Improper use of terminology
You include the sentence: "Another logic state is ‘Z’ also referred to as 'tri- state.' " The term 'Z' is not complete. 'Z' is the mathematical label for impedance. The term 'Hi-Z' is the correct logical term for high impedance when refering to a tri-state output. Therefore, the three valid states of a tri-state capable gate are: '0', '1', 'Hi- Z'. Just using the letter 'Z' is not common practice. The term 'Tri-State'refers to the gate's ability to provide three states. It does not implicitly mean the third (or Hi-Z) state. However, there is a general tendency to make statements like "Tri-state the output" when the intended message is "Set the output to Hi-Z"
- Tobin Gimber, Haldex Hydraulics Corp.. tobin.gimber@haldex.com - Jan 10, 2005