Digital Waveform Timing

This tutorial is part of the National Instruments Measurement Fundamentals series. Each tutorial in this series, will teach you a specific topic of common measurement applications, by explaining the theory and giving practical examples. This tutorial covers the timing characteristics of digital signals.
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For information about voltage levels of digital signals, refer to the Digital Measurements: Logic Families, Digital Level and Drive States tutorial.

For the complete list of tutorials, return to the NI Measurement Fundamentals Main page.

Introduction to Digital Signals

A logic level says which bit (0 or 1) is being carried. However, for communication between different devices, the bits indicated by the levels should be associated with some timing information. In order to achieve this, digital waveforms are referenced to clock signals. A basic clock signal is a square wave with a fixed period, labeled t_P on Figure 2 below. The period is measured from one edge of the clock (usually the rising edge) to the next similar edge of the clock (i.e. the next rising edge). The frequency of the clock can be calculated by the inverse of the clock period; that is 1/t_P.

Clock signals are used to synchronize digital transmitters and receivers during data transfer. For example, the transmitter can use each rising edge of the clock signal on Figure 2 to send each bit of data and the receiver can use the same clock to read the data.



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Timing of Digital Signals

Active Digital Edge
Digital transmitters drive new data samples on each “assertion” edge of the clock also called active clock edge. For some devices, the assertion edge is the rising edge (from low to high); for others it is the falling edge (from high to low). Some newer devices even use both the rising and the falling edge of the clock; these devices are called Double Date Rate (DDR) devices. In actuality, the data is transmitted after a small delay from the assertion edge of the clock; this delay is called the clock-to-out time or t_CO.

Receivers sample data on each active clock edge. In the example on Figure 2, the assertion edge is shown by the vertical arrow lines to be the rising edge of the clock.

Hold and Setup Time
When a receiver samples the data on the digital lines based on the assertion edge of the receiver’s clock, there are two timing parameters that must be carefully understood in order for the receiver to latch the data reliably. The basic principle is these data lines must not change during the sampling time.

The first of these parameters is called the setup time or t_SU. Setup time refers to the amount of time that the data signals must be stable (that is, must not change) before the assertion edge of the receiver’s clock. The second parameter is hold time, abbreviated t_H. Hold time is the amount of time that the data signals must be stable after the assertion edge of the receiver’s clock. Together, the set-up time and the hold time serve to require a stable window around the assertion edge of the receiver’s clock for the receiver to reliably sample the data. If the setup times and hold times of a receiver are not met, the data will not be sampled reliably. Even worse, the receiver can go into an unstable state.



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Timing Errors and Analysis

Timing is one of the most important factors in digital systems. The reliability and accuracy of digital communications are based upon the quality of its timing. In real world digital communication systems, there are numerous timing errors. Two of the most important ones are Jitter and Drift.

Jitter
Jitter is the deviation from ideal timing of an event, and is typically measured from the zero-crossing of a reference signal. Jitter typically comes from cross-talk, simultaneous switching outputs, and other regularly occurring interference signals. Since jitter varies over time, measurements and quantification of jitter can range from a visual estimate on a scope of the range of jitter in seconds, to a statistical-based measurement such as one based on the standard deviation over time.

Drift
Clock drift occurs when the transmitter’s clock period is slightly different from that of the receiver. After many clock cycles, the difference between the two periods becomes noticeable and may cause loss of synchronization and other errors. For example, given two high-speed digital I/O devices acquiring at 100 MHz, the real oscillators on the instruments will each have a rate slightly different from that of its counterpart. Typically, clock accuracy is specified in parts per million (ppm) or parts per billion (ppb). For example, a 100 MHz clock with 25 ppm accuracy would run at a rate of 100 MHz +/- 2.5 kHz. If the two digital I/O devices are acquiring data for 5 seconds at that rate and accuracy, they could be out of synchronization by up to 500 µs, or 5 clock periods, after 5 seconds of acquisition.

Eye Diagram
An eye diagram is constructed by looking at the outputs of a digital transmitter over three time periods. These three time periods are three periods of the main system clock, t_P, demarked by the blue vertical dashed lines on Figure 5. If the transmitter outputs three logical ‘0’ value over the time period, the plot might look like the green plot on Figure 5. An eye diagram, shown in figure 5, is constructed by overlaying all of the possible combinations of 0’s and 1’s (0 1 1 in pink, 1 1 0 in yellow, 0 0 1 in blue, 1 0 0 in green ) on single plot.

The Eye Diagram is a timing analysis tool providing the user with a good visual of timing and level errors. See Figure 6. In real life, errors like Jitter are very difficult to quantify since they change so often and are so small. Therefore, an eye diagram is a very good tool for finding the maximum Jitter as well as voltage level errors. As these errors increase, the white space in the center of the eye diagram decreases. That space is defined by two characteristics; the eye width and the eye height.

The width of the white space of the final eye diagram is called, simply enough, the eye width. If an eye diagram is composed of enough samples (millions and millions of three time period transitions), the eye width is a good measure of the amount of time, in any given time period, that the data lines are stable. This can give a good idea of how much setup time and hold-time is allowable.

The height of the white space of the final eye diagram is called the eye height. If an eye diagram is composed of enough samples (millions and millions of three time period transitions), the eye height can tell where the receiver’s V_IH and V_IL need to be to sample the data correctly.

The better quality the digital signal transmission, the more open white space there should be in the eye. Said differently, the eye width and eye height should be as large as possible.




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Example of Digital Signals Timing Analysis

A real eye diagram, displayed in Figure 8, is an intensity plot of the overlaid transitions sampled by high-speed digitizer, such as the NI 5124 200 MS/s digitizer. The color of the plot is a measure of the percentage of overlaid transitions for any given pixel. The eye diagram, shown in Figure 8, is represented by the following:

1. Point where the overlaid data transitions cross the V_IH of the receiver. This is the earliest time that the clock could occur to guarantee reliable data sampling. If the clock were any earlier, the data lines could still be changing during the required set-up time period. In this system the V_IH voltage level is the limiting level.
2. This intersection marks the valid point for the clock assertion time + the clock hold time.
3. Receiver’s setup time
4. Receiver’s hold time
5. Low percentage of the overlaid transitions
6. Very high percentage of the transitions

• The assertion edges of the receiver’s clock is the vertical, solid, lines
• The receiver’s V_IH and V_IL are represented by the horizontal dashed lines
  

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Relevant NI Products

Customers interested in this topic were also interested in the following NI products:

• LabVIEW Graphical Programming Environment
• SignalExpress Interactive Software Environment
• NI Modulation Toolkit
• High-Speed Digital I/O
• Digital Multimeter (DMM)
• Data Acquisition (DAQ)
• Counter/Timer devices

For the complete list of tutorials, return to the NI Measurement Fundamentals Main page.

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