Factors to Consider When Clocking the TNT4882 at Frequencies Less Than 40 MHz

TNT4882 designs normally use a 40 MHz CLOCK signal. Clocking at lower frequencies has little effect besides slowing down some internal functions.

This document describes some TNT4882 aspects for you to consider when you clock the chip slower than 40 MHz.

HS488 Functions

The HS488 functionality of the TNT4882 does not work properly unless the TNT4882 is clocked at 40 MHz. The HSE bit (MISC[4]) enables HS488, so if the clock signal frequency is less than 40 MHz, you should not set the HSE bit.

WR* Signal Recovery Time

Some TNT4882 registers have no storage elements. When the application program writes to one of these registers, the TNT4882 generates command message pulses. For example, when you write a 10 (hex) to the Command Register (CMDR), the internal Reset FIFO message asserts and then unasserts.

The following registers generate command message pulses:

• CMDR (used in all modes)
• AUXMR (used in Turbo+7210 and one-chip modes)
• AUXCR (used only in Turbo+9914 mode)
  

The CLOCK signal controls the pulsing. To ensure proper operation, make certain that at least four CLOCK periods separate any two consecutive writes to one of these registers. Figure 1 illustrates the time between two writes to the Auxiliary Mode Register (AUXMR), the Auxiliary Command Register (AUXCR), or the CMDR.

T_w1 must be at least four CLOCK periods.

T1 Delay -- Byte Sourcing Speed

The ANSI/IEEE Standard 488.1-1987 requires that when a device is sourcing (sending) commands or data, the GPIB data bus (DIO[8:1]*) must be stable for a time, T1, before the device can assert DAV*.

The TNT4882 uses the CLOCK signal to generate the T1 delay. If the clock frequency of the TNT4882 is lower than 40 MHz, you can set the T1 delay to wait for fewer CLOCK cycles.

When the TNT4882 is sourcing data or commands, the status of the bits described in Table 1 and Table 2 determines the T1 delay.

USTD	TRI	MSTD	PT1_ENA	T1 Delay (in CLOCK Periods)
				First Byte	Other Bytes
0	0	0	0	80	80
1	0	0	0	44	44
X	1	0	0	44	20
X	X	1	0	44	14
X	X	X	1	44	Programmable

stdl	vstdl	PT1_ENA	T1 Delay (in CLOCK Periods)
			First Byte	Other Bytes
0	0	0	80	80
1	0	0	44	44
1	1	0	44	20
1	0	1	44	Programmable

PT1_ENA and the programmable T1 delay can be set by writing to the PT1 register. Notice that PT1_ENA can be set only when the TNT4882 is in Turbo+7210 mode or one-chip mode. If you want to use PT1_ENA in Turbo+9914 mode, you must change to Turbo+7210 mode, set PT1 enable, then change back to Turbo+9914 mode. See the Changing the TNT4882 Architecture Modes section in Chapter 2 of your TNT4882 reference manual.

Because the TNT4882 uses tri-state GPIB transceivers for the DAV, EOI, and DIO signals, the IEEE 488.1 standard specifies the following requirements for the T1 delay:

• On the first data byte, T1
• On other data bytes, T1
• If one GPIB device load exists for every meter of cable, T1 ³ 350 ns for every byte after the first.

Internal Timer
The TNT4882 internal timer uses the CLOCK signal to generate its timer delays. At lower CLOCK frequencies, the timer runs slower. For a formula to calculate the timer delays in Turbo+9914 mode, see the Accessory Register J (ACCRJ) section in Chapter 3 of your TNT4882 reference manual. For a formula to calculate the timer delays in Turbo+7210 or one-chip mode, see the Auxiliary Register J (AUXRJ) section in Chapter 3 of your TNT4882 reference manual.

Controller Function
Part of the Controller function depends on the CLOCK frequency. The IEEE 488.1 standard requires that the Controller function meet certain delays when it changes from Standby to Active Controller. Because these delays are not programmable, the TNT4882 takes longer to go from Standby to Active Controller if the CLOCK frequency is less than 40 MHz.

IFC and REN Signals
The TNT4882 can take up to four CLOCK periods to respond to changes in the IFC or REN signals. The IEEE 488.1 standard requires that these signals be asserted or unasserted for at least 100 µs before changing. Unless the TNT4882 CLOCK frequency is very low (< 200 kHz), the chip responds properly.

RDY Signal
When the application software reads or writes to one of the original 9914 or 7210 registers, the hardware must extend the I/O cycle until the RDY pin asserts. The RDY pin may take up to 10 CLOCK periods to assert.

See the description of the RDY pin that is in Chapter 6 of your TNT4882 reference manual.

DRQ Timer
The TNT4882 supports DMA reads and writes to the internal FIFOs. The DRQ pin asserts when the FIFOs have data to read or write.

The Timer Register (TIMER)—not the ACCRJ or AUXRJ—can limit the time DRQ remains asserted. If the TIMER is used in timeout mode, the DRQ timer increments once every four CLOCK cycles.

See the Timer Register (TIMER) section in Chapter 3 of your TNT4882 reference manual for a more detailed description of the DRQ timer.

Interrupts
Several interrupting conditions depend on the CLOCK signal. The delay from when an interrupt condition is true until the INT pin asserts may be longer if the TNT4882 CLOCK frequency is less than 40 MHz.

Acceptor Functions
The TNT4882 uses the CLOCK signal in its acceptor handshake function. The chip accepts bytes at a slower rate if the CLOCK frequency is less than 40 MHz.

Trigger Pulse Width
When the control program writes the trig auxiliary command to the AUXMR, the TNT4882 pulses the TRIG pin. The pulse width of the TRIG signal is one CLOCK period.
Related Links:
TNT4882 Programmer Reference Manual

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