High-Speed Digital I/O Voltage Levels

This tutorial is part of the National Instruments Measurement Fundamentals series. Each tutorial in this series, will teach you a specific topic of common measurement applications, by explaining the theory and giving practical examples. This tutorial covers the voltage levels of digital signals.

You can also view an interactive presentation (10min video) that takes you through this tutorial's material at your own pace.

For additional digital only concepts, refer to the Digital I/O Fundamentals main page.
For the complete list of tutorials, return to the NI Measurement Fundamentals Main page.

Voltage Levels Overview

Digital devices have voltage levels specified for normal operation of their acquisition and generation operations. Voltage levels for a digital I/O device are what defines how a device determines a valid logic state (logic high level or logic low level). Voltage levels are defined differently depending on whether you are discussing a single-ended or differential device.

Single-ended Digital I/O Voltage Levels

For single-ended signals, voltage levels are usually specified in terms of the voltage placed on the output terminal when driving a high level signal or when driving a low level signal, and by the voltage required on the input terminal for the signal to be recognized as a high or low level signal. In general, the single-ended voltage levels are defined as follows:

• Generation Voltage High Level (V_OH) - when configured for active drive generation, this is the voltage produced at the channel electronics when the Pattern Generation Engine generates a binary one. When configured for open collector generation, Generation Voltage High Level is equivalent to setting the data channel to a high-impedance state.
• Generation Voltage Low Level (V_OL) — the voltage produced at the channel electronics when the Pattern Generation Engine generates a binary zero.
• Acquisition Voltage High Level (V_IH) —the voltage level at or above which the Pattern Acquisition Engine senses a binary one.
• Acquisition Voltage Low Level (V_IL) - the voltage level at or below which the Pattern Acquisition Engine senses a binary zero.

When connecting a digital module to a device under test (DUT), you must ensure that the interface voltage levels are compatible. The relationship between the single-ended voltage levels and the DUT voltage levels are shown figure 1.
To accurately communicate with a DUT, configure the digital device such that the following conditions are met:

· Generation Voltage High Level ≥ DUT V_IH
· Generation Voltage Low Level ≤ DUT V_IL
· Acquisition Voltage High Level ≤ DUT V_OH
· Acquisition Voltage Low Level ≥ DUT V_OL
· Acquisition Voltage High Level > Acquisition Voltage Low Level

The extra margin between the voltage level being driven by the source and the voltage level required at the destination is known as the noise immunity margin (NIM).
The NIM indicates the amount of noise tolerable on the connecting cable with a data bit being received in correctly. The total NIM is computed as:

NIM = [min (|Generation Voltage High - DUT V_IH|, |Generation Voltage Low - DUT V_IL|,
|DUT V_OH - Acquisition Voltage High|, |DUT V_OL - Acquisition Voltage Low|)]

One way to protect against external noise sources is using a shielded cable. However, if your system operates in a particularly noisy environment and has having difficulty with incorrect data bits, you may want to consider increasing the NIM, if possible.

Visit the Digital I/O Logic Family Tutorial to learn about the different classifications of singled-ended digital I/O signals.

Differential Digital I/O Voltage Levels

Unlike single-ended signals, differential signals are transmitted in parity. That is, instead of a single conductor referenced to ground, two conductors, referenced to each other, are used to transmit data. The digital driver still drives out two voltages, as in the single-ended case. The receiver, however, interprets the signals based on the voltage difference between the pair of signals – not on a reference to ground. For the differential digital signal to be interpreted as a binary 0, the signal must be less than its complementary signal by more than a particular value (V_TH in figure 2). V_TH varies and is specified by the particular logic family. Since the conductors are referenced and transmitted together, you can achieve higher noise immunity in your signals. A benefit to this is that you can allow much smaller signal swings, which enables you to transmit data much farther, much faster, and at a fraction of the power.

Since differential signals reference a positive signal to a complementary signal, across a specified differential impedance, voltage levels are typically specified from a differential, rather than an absolute, perspective (depending on the standard). For example, the absolute voltage levels of an LVDS transmission pair across a 100Ω differential terminating impedance may have a V_OH of 1.4 V on the positive conductor and a V_OL of 1.1 V on the complementary conductor. The differential voltage would then be called out as the difference between the two—300 mV (shown as V_OD in figure 2). There is, however, a common mode component of the signal (shown as V_OS in figure 2) which is also called out by most differential specifications and is referenced to common.

In general, the differential voltage levels are defined as follows:

• Differential Output Voltage (V_OD)—the difference in voltage between the positive and complementary conductors of a differential transmission. Can be thought of as the difference of the two conductors.
• Offset Voltage (V_OS)—the common mode of the differential signal. Can be though of as the average of the two conductors.
• Threshold Voltage (V_TH)—the differential voltage threshold at which the receiver registers a valid logic state.
• Input Voltage Range (V_RANGE)—the absolute voltage, referenced to common, allowed by the receiver.

When connecting a digital I/O module to a device under test (DUT), you must ensure that the interface voltage levels are compatible. The relationship between the differential device voltage levels and the DUT voltage levels are shown in figure 2.
The extra margin between the voltage level being driven by the source and the voltage level required at the destination is known as the NIM. The NIM indicates the amount of noise tolerable on the connecting cable with a data bit being received in correctly. The total NIM is computed as:

NIM = [min (|Generation V_OD - DUT V_TH| , |DUT V_OD - Acquisition V_TH|)]

Visit the Digital I/O Logic Family Tutorial to learn about the different classifications of differential digital I/O signals.

Relevant NI Products

Customers interested in this topic were also interested in the following NI products:

• High-Speed Digital I/O
• Industrial Digital I/O
• Logic Analyzers
• Modular Instruments (digital multimeters, digitizers, switching, etc...)
• Digital Waveform Editor
• LabVIEW Graphical Programming Environment
• SignalExpress Interactive Software Environment

For the complete list of tutorials, return to the NI Measurement Fundamentals Main page

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