Integrating IP Cores into LabVIEW FPGA with the HDL Interface Node

This document describes how to integrate an IP core into a LabVIEW application using the HDL Interface Node in LabVIEW FPGA Module. For general information about LabVIEW FPGA Module, refer to the white paper Developing Measurement and Control Applications with LabVIEW FPGA and Reconfigurable I/O (see Related Links.)

The HDL Interface Node

The HDL Interface Node is a feature introduced in LabVIEW 7.1 FPGA Module. It enables users to integrate VHDL into a LabVIEW FPGA VI. You can enter VHDL code directly into the HDL Interface Node, or you can refer to external .vhd files. For a more detailed description the HDL Interface Node and how to use it, refer to the LabVIEW FPGA Module documentation.

IP Cores

A core is a subcomponent of a HDL design. It provides functionality such as filtering or implementing communication protocols. You can obtain cores from a variety of sources, and many are available free of charge. This document describes how to create an application similar to the FPGAFilter application in the zip file linked below. This application instantiates a Xilinx distributed-arithmetic, 10 kHz lowpass, FIR filter core in LabVIEW FPGA Module using the HDL Interface Node. Documentation for this core can be found by clicking on the Xilinx Distributed Arithmetic Filter Core Documentation link below.

See Also:
Xilinx Distributed Arithmetic Filter Core Documentation

Installing Xilinx ISE

Before using the Xilinx Core Generator, you must have Xilinx ISE properly installed. If you just installed LabVIEW FPGA, you do not have all the Xilinx system variables set. Xilinx tools distributed with LabVIEW FPGA are to be used in conjunction with the purchase and installation of LabVIEW FPGA only. Run <Drive letter>:\nifpga11\xilinx\bin\nt\setXenv.bat to properly install the Xilinx tools. Click on the “no” button when asked about parallel cable drivers. Note that after running this installer, you will have to uninstall Xilinx ISE from ‘Add/Remove Programs’ should you wish to uninstall Xilinx ISE (the Xilinx tools will no longer be automatically uninstalled by the LabVIEW FPGA Module uninstaller.)

Designing the Filter

The first step in using the filter core is to generate the filter coefficients and store them in a .coe file format. You will be able to load this file into the configurator of the filter core. You can generate the coefficients manually or can use various tools to help with this process. You may use Generate Coefficient.vi example in the file FilterDesign.zip attached below to create the coefficients. Open GenerateCoefficient.vi. Notice that the front panel control defaults are set to generate a 10 kHz lowpass filter. The VI also quantizes the generated coefficients and scales them to integers. Run the VI and save the coefficients into file named 10Kcutoff.coe.The resulting response is shown on the front panel. It is always a good idea to check the filter response after quantization.

Generating the Netlist

Now that you have generated the filter coefficients, you are ready to configure the core. Launch the Xilinx Project Navigator from the Xilinx ISE 6 program group. Follow the steps below to configure the core and generate the netlist.

1. Select File > New Project to bring up the New Project window. Name your project filt and select HDL for Top-Level Module Type. Click the Next button.
2. Set the Values to match those shown below and click the Next button.

3. When prompted to “Create a New Source”, press the “New Source” button. Note the filt.npl project file linked below already has these steps completed.
4. Select IP (CoreGen & Architectur Wizard) as the type and name the new source filt.
5. You will then be presented with a tree view of all available cores. These are included in your installation of the Xilinx toolset and Project Navigator will automatically load them from your drive. Select Digital Signal Processing > Filters > Distributed Arithmetic FIR Filter. Click the Next button and then Finish.

6. You will not need to add any additional sources, so you can click the Next button in the following two dialog boxes, and then click the Finish button. This will bring up the configurator for the filter core.
7. Enter filt for the Component Name and configure as shown below. Then click the Next button.

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8. For Number of Taps, enter 53 if you are using the included example files, or if you created your own filter, use the actual number of coefficients. Similarly, if you are using the example files, Impulse Response should be set to Symmetric and Coefficient Width should be set to 14 bits as shown below.

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Click the Load Coefficients button to load either the example .coe filt.coe, or the one you created. Click the Next button.
9. Set Input Data Width to 16 bits and configure as shown below. Then click the Generate button. After generation, you will have a filt.vhd and filt.edn file in the project directory that define the core's interface and implementation respectively. You can view example files in the attached zip file CoreConfig.zip.

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Integrating the Core into a LabVIEW FPGA VI

You have now generated everything you need to integrate the filter core into a LabVIEW FPGA VI. The following steps will discuss how to use the files you just created to configure the HDL Interface Node.

1. Launch LabVIEW and target your RIO device. Create a new project and new VI, then place an HDL Interface Node from the LabVIEW FPGA Advanced palette onto the block diagram. Double-click on the node to configure it.
2. In the Parameters tab of the HDL Interface Node configuration dialog, double-click in the Names column to add parameters. Create parameters as shown below.
3. Next, switch to the Code tab. Notice that your parameters now appear in the entity section. To complete the next two sections of code, you will need to refer to the filt.vhd file that you generated earlier and interface the filter core to the LabVIEW FPGA execution system.
4. To view the completed example, open the UsingFilterCore.vi VI attached in the file UsingCore.zip and study the code in the HDL interface node. Here is where we have interfaced the LabVIEW execution chain to the execution of the core. The filter core interfaces nicely because there is a nd (new data) flag that tells the core when the current sample should be processed and there is a rdy (ready) flag that tells the user when data is available. This roughly corresponds to the LabVIEW FPGA enable_in and enable_out. The main difference is the enable signals are constant high when asserted while nd and rdy are pulsed. The code surrounding the core’s instantiation creates a pulse for nd on the first clock cycle of an assertion of enable_in and then holds enable_out high when rdy asserts. Enable_out must be driven low when enable_clr asserts. This provides for looping capability.
5. Next, switch to the External Files tab. Click the Add File button and select the filt.edn file that you created earlier. This is the EDIF netlist file that you generated earlier.
6. Next, click the OK button to configure the HDL Interface Node. You have now integrated the filter core into LabVIEW. Refer to the UsingFilterCore.vi block diagram for an example of how to use the core to filter analog data with your RIO hardware.


Related Links:
Developing Measurement and Control Applications with the LabVIEW FPGA Module and Reconfigurable I/O Devices

On-Demand Training: Importing External Codes to LabVIEW FPGA Using CLIP (SSP Required)

Downloads

core_config.zip

using_core.zip

filter_design.zip

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Relevance to newer versions of Labview FPGA
Couled this article be updated to include newer versions of Labview FPGA? Especially with regard to installing the Xilinx Tools for LV8.5 and 8.6.
- Shailesh Joshi, fka. joshi@fka.de - Oct 24, 2008