NAT4882 CLOCK Signal Considerations

This document describes requirements and considerations for the CLOCK pin of the NAT4882 GPIB Controller ASIC. This document is intended for use as a supplement to the NAT4882 Programmer Reference Manual (linked above).

CLOCK Signal Requirements

CLOCK signal requirements for the NAT4882 include the following:

• The CLOCK pin is a TTL input.
• The NAT4882 does not function properly without a CLOCK signal.
• The rising and falling edges of the CLOCK signal must be monotonic.
• The minimum pulse width of the CLOCK signal high or low (Tpw in Figure 1) is 15 ns.
• National Instruments does not specify the maximum rise or fall time of the CLOCK signal (Trf in Figure 1). Using a signal with unusually slow rise and fall times might adversely affect power consumption.

NAT4882 designs normally use a 20 MHz CLOCK signal. Clocking at lower frequencies has no effect except for slowing down some internal functions. The following sections describe some aspects of the NAT4882 to consider when clocking the chip at frequencies less than 20 MHz.

WR* Signal Recovery Time
The WR* signal recovery time is the most important consideration for guaranteeing proper operation of the NAT4882.

When the control program writes to the Auxiliary Mode Register (7210 Mode) or Auxiliary Command Register (9914 Mode), the NAT4882 generates command message pulses. For example, when you write a 6 to the Auxiliary Mode Register, the seoi (Send EOI with next byte) local message asserts and then unasserts. Internal state machines respond to the pulsed messages.

The CLOCK signal controls the pulsing. To guarantee proper operation, make sure that there are four CLOCK periods between consecutive unassertion edges of the WR* signal. Figure 2 illustrates the time between two writes to the AUXMR or AUXCR (Tw1).


Tw1 must be at least four CLOCK periods. Commands should be issued at intervals of at least 200 ns (four CLOCK cycles at 20 MHz).

T1 Delay: Byte Sourcing Speed
ANSI/IEEE Standard 488.1-1987 requires that when a device is sourcing (sending) commands or data, the GPIB data bus (DIO[8:1]*) must be stable for a time, T1, before the assertion of DAV*.

The NAT4882 uses the CLOCK signal to generate the T1 delay. If the CLOCK frequency of the NAT4882 is less than 20 MHz, you can set the T1 delay to wait for fewer CLOCK cycles.

When the NAT4882 is sourcing data or commands, the status of the bits described in the following table determines the T1 delay (in 7210 mode).

MSTD1	TRI2	USTR3	T1 Delay (in CLOCK Periods)
			First Byte	Other Bytes
0	0	0	40	40
0	0	1	22	22
0	1	0	40	10
0	1	1	22	7
1	1	1	22	4
1Bit 5 of the Key Control Register
2Bit 2 of Auxiliary Register B
3Bit 3 of Auxiliary Register 1

Many designs use tri-state GPIB transceivers for the DAV, EOI, and DIO signals. The 75162 and 75160 integrated circuits provide tri-state transceivers for these signals. If a GPIB device uses tri-state transceivers, IEEE 488.1 makes the following requirements for the T1 delay:

• On the first data byte, T1 ³ 1100 ns.
• On other data bytes, T1 ³ 500 ns.
• If there is one GPIB device load for every meter of cable, T1 ³ 350 ns for every byte after the first.

If a GPIB device does not use tri-state GPIB transceivers, T1 must be ³ 2000 ns for every byte.

Note: If the CLOCK period is more than 2000 ns (1100 ns with tri-state transceivers), you can set the NOT1 bit (Key Control Register bit 4). When the NOT1 bit is set, the NAT4882 T1 delay is between one and two CLOCK periods, and the NAT4882 ignores the status of the MSTD, TRI, and USTD bits.

Internal Timer
The NAT4882 internal timer uses the CLOCK signal to generate its timer delays. At lower CLOCK frequencies, the timer runs slower. Use the following formula to compute the timeout value:
Controller Function
Two parts of the Controller functions depend on the CLOCK frequency. IEEE 488.1 requires that the Controller function meet certain delays when going from Standby to Active Controller. Because these delays are not programmable, the NAT4882 takes longer to go from Standby to Active Controller if the CLOCK frequency is less than 20 MHz. To learn how to use the CO bit to determine when the chip has become Active Controller, refer to the Going from Standby to Active Controller section in Chapter 3, NAT4882 Programming Considerations, of the related link, NAT4882 Programmer Reference Manual.

In 7210 Mode, the Controller also uses the CLOCK signal to generate delays used when conducting a parallel poll. When the control program writes the rpp (Request Parallel Poll) auxiliary command to the Auxiliary Mode Register, the NAT4882 conducts a parallel poll. The NAT4882 normally completes the parallel poll after a delay of at least 40 CLOCK periods.

Acceptor Functions
The NAT4882 uses the CLOCK signal in its acceptor handshake function. The chip accepts bytes at a slower rate if the CLOCK frequency is less than 20 MHz.

Trigger Pulse Width
When the control program writes the TRIG auxiliary command to the Auxiliary Mode Register, the NAT4882 pulses the TRIG pin. The pulse width of the TRIG signal is one CLOCK period.

Interrupts
Several of the interrupting conditions depend on the CLOCK signal. The delay from when an interrupt condition is true until the INT pin asserts may be longer if the NAT4882 CLOCK frequency is less than 20 MHz.

IFC and REN Signals
The NAT4882 can take up to four CLOCK periods to respond to changes in the IFC or REN signals. IEEE 488.1 requires that these signals be asserted or unasserted for at least 100 µs before changing. Unless the NAT4882 CLOCK frequency is very low (< 100 kHz), the chip responds properly.
Related Links:
NAT4882 Programmer Reference Manual

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