NAT4882 GPIB Synchronization Detection Supplement

This technical note supplements the description of GPIB synchronization that is given in the NAT4882 Programmer Reference Manual (part number 320383-01). This technical note refers to and gives additional information about register bits that are described in the reference manual and the IEEE 488.2 Controller: NAT4882BPL Data Sheet (part number 340495-01). You should also refer to the ANSI/IEEE Standard 488.1-1987 for more information about the GPIB.

Consult the NAT4882 Programmer Reference Manual for a detailed description or definition of the register and bit names and mnemonics that this technical note uses.

GPIB Synchronization

The GPIB is synchronized when all devices participating in a data transfer have accepted the last byte of the data transfer. At the end of a transfer, you should typically wait for the GPIB to be synchronized before you initiate more bus activity.

While the NAT4882 is in 7210 compatibility mode, you can use the Synchronization (SYNC) bit (ISR0[0]) to determine when the GPIB is synchronized. The SYNC bit is not available when the NAT4882 is in 9914 compatibility mode.

The behavior of the SYNC bit depends on whether you are using DMA to transfer data to or from the NAT4882. The SYNC bit behavior also depends on whether the NAT4882 is receiving data (as a GPIB Listener) or sending data or commands (as a GPIB Talker or Controller).

Using SYNC -- GPIB Reads Using DMA

To use the SYNC bit during DMA reads, the host interface must use the TC pin of the NAT4882. On the last byte of a DMA transfer, the host interface should simultaneously assert the TC pin and the DMA Acknowledge (DACK*) pin. If the host interface does not use the TC pin, do not use the SYNC bit for DMA transfers.

To use the SYNC bit during DMA reads, complete the following steps:

1. Make DMAO = 0 and DMAI = 1 by writing to Interrupt Mask Register 2 (IMR2) during the initialization of a DMA GPIB read transfer.

2. Issue the clearSYNC auxiliary command by writing to the Auxiliary Mode Register (AUXMR). This write clears the SYNC bit.

3. Start the DMA transfer.

4. Begin polling for the SYNC bit or set the Synchronization Interrupt Enable (SYNC IE) bit to interrupt when SYNC sets.

At the end of the DMA transfer, the host interface reads a byte from the Data In Register (DIR) by simultaneously asserting the DACK*, RD*, and TC pins of the NAT4882. The SYNC bit sets when all devices participating in the transfer accept that byte.

Using SYNC -- GPIB Writes Using DMA

To use the SYNC bit during DMA writes, the host interface must use the TC pin of the NAT4882. On the last byte of a DMA transfer, the host interface should simultaneously assert the TC pin and the DACK* pin. If the host interface does not use the TC pin, do not use the SYNC bit for DMA transfers.

To use the SYNC bit during DMA writes, complete the following steps:

1. Make DMAO = 1 and DMAI = 0 by writing to the IMR2 during the initialization of a DMA GPIB write transfer.

2. Issue the setSYNC auxiliary command by writing to the AUXMR. This write sets the SYNC bit and forces a reset of the synchronization detection circuitry.

3. Issue the clearSYNC auxiliary command by writing to the AUXMR. This write clears the SYNC bit.

4. Start the DMA transfer.

5. Begin polling for the SYNC bit or set SYNC IE to interrupt when SYNC sets.

At the end of the DMA transfer, the host interface writes a byte to the Command/Data Out Register (CDOR) by simultaneously asserting the DACK*, WR*, and TC pins. The SYNC bit sets when all devices participating in the transfer accept that byte.

Using SYNC -- GPIB Reads Not Using DMA

To use the SYNC bit when the GPIB reads are not using DMA, complete the following steps:

1. Make DMAO = 0 and DMAI = 0 by writing to the IMR2 during the initialization of a non-DMA GPIB read transfer.

2. Issue the setSYNC auxiliary command by writing to the AUXMR.

3. Start the transfer.

The NAT4882 must be an Active or Addressed GPIB Listener (see the Listener Active, or LA, bit, ADSR[2]). During the transfer, SYNC clears when the talking device begins to transfer a character. SYNC sets when all devices participating in the transfer accept the byte. SYNC clears and sets with each byte of the transfer. After you read the last byte of the transfer out of the DIR, begin polling the SYNC bit to determine when the GPIB is synchronized.

The NAT4882 can also interrupt on SYNC if the SYNC IE bit (IMR0[0]) is set. Do not set SYNC IE until after you read the last byte of the transfer out of the DIR.

For non-DMA GPIB reads, notice that the condition that sets SYNC is not the same as the condition that sets DI (IMR1[0]). DI asserts when the NAT4882 accepts a byte; SYNC asserts when the NAT4882 and all other accepting devices accept a byte.

Using SYNC -- GPIB Writes Not Using DMA

You can use the SYNC bit when the NAT4882 is sending data as a GPIB Talker or when the NAT4882 is sending commands as a GPIB Controller. To use the SYNC bit, complete the following steps:

1. Make DMAO = 0 and DMAI = 0 by writing to the IMR2 during the initialization of a non-DMA GPIB write transfer.

2. Issue the setSYNC auxiliary command by writing to the AUXMR.

3. Transfer all the bytes of the messages--except for the last byte--in the normal manner. The SYNC bit remains set during the transfer of these bytes.

4. Issue the clearSYNC auxiliary command by writing to the AUXMR before you write the last byte of the message to the CDOR. This write clears the SYNC bit.

5. Write the last byte of the message to the CDOR.

6. Begin polling for the SYNC bit or set SYNC IE to interrupt when SYNC sets.

The SYNC bit sets when all devices participating in the transfer accept the last byte.

SYNC IE Recommendation

In the interrupt handler that processes SYNC interrupts, clear the SYNC IE bit to disable the interrupt. Do not issue the clearSYNC auxiliary command. Clearing SYNC IE guarantees that no SYNC interrupts will occur.

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