NAT4882 Pin Description Supplement

This document supplements the pin descriptions that are given in the IEEE 488.2 Controller: NAT4882BPL Data Sheet (part number 340495-01). This document refers to and gives additional information about register bits that are described in the data sheet and the NAT4882 Programmer Reference Manual (see the related link); this document does not discuss any new pins. You should also refer to the ANSI/IEEE Standard 488.1-1987.

GPIB Device Status Pins

The NAT4882 has seven device status pins: Controller-In-Charge (CIC), Talker Addressed (TA), Listener Addressed (LA), Trigger (TRIG), Remote (REM), Lockout (LOK), and My Address (MA). These pins reflect the status of some IEEE 488.1 functions.

All the device status pins are output-only pins. These pins can drive LEDs or other status indicators. If the application hardware does not have a use for a status pin, you can leave the status pin unconnected.

Controller-In-Charge (CIC) Signal
The CIC pin asserts when the CIC bit sets. The CIC bit is bit 7 of the Address Status Register (ADSR[7]) in 7210 mode. The CIC bit is bit 0 of the Interrupt Status Register 2 (ISR2[0]) in 9914 mode. CIC asserts when the NAT4882 is an Active or Standby Controller. CIC unasserts when the NAT4882 is an Idle Controller.

When the NAT4882 is the Active Controller, it asserts the IEEE 488 ATN* signal. As an Active Controller, the NAT4882 can send remote multiline messages (commands) and conduct serial and parallel polls.

When the NAT4882 is the Standby Controller, it does not assert the IEEE 488 ATN* signal. When the NAT4882 is the Standby Controller, the IEEE 488 Addressed Talker can send data to the IEEE 488 Addressed Listener.

Referring to the IEEE 488.1 Controller function: CIC = ~(CIDS + CADS)

Talker Addressed (TA) Signal
The TA pin asserts when the TA bit (ADSR[1]) sets. The TA pin indicates that the NAT4882 is an Active or Addressed IEEE 488 Talker. TA also asserts when the NAT4882 is responding to a serial poll. As an IEEE 488 Talker, the NAT4882 can send data to other devices.

Referring to the IEEE 488.1 Talker function: TA = TADS + TACS + SPAS

Listener Addressed (LA) Signal
The LA pin asserts when the LA bit (ADSR[2]) sets. The LA pin indicates that the NAT4882 is an Active or Addressed IEEE 488 Listener. As an IEEE 488 Listener, the NAT4882 can receive data from the IEEE 488 Active Talker.

Referring to the IEEE 488.1 Listener function: LA = LADS + LACS

Trigger (TRIG) Signal
The TRIG pin asserts when the NAT4882 is in the IEEE 488 Device Trigger Active State (DTAS). The NAT4882 enters the DTAS when it is an Addressed Listener and is receiving the Group Execute Trigger (GET) command from the Active Controller.

The TRIG pin also pulses when the trig auxiliary command is written to the Auxiliary Mode Register (AUXMR) in 7210 mode or when the fget auxiliary command is written to the Auxiliary Command Register (AUXCR) in 9914 mode.

Remote (REM) Signal
The REM pin asserts when the REM bit asserts. The REM bit is bit 4 of the Interrupt Status Register 2 (ISR2[4]) in 7210 mode. The REM bit is ADSR[7] in 9914 mode. REM asserts when the NAT4882 GPIB Remote/Local (RL) function is in either Remote State (REMS) or Remote With Lockout State (RWLS).

When REM asserts, some or all of the local device controls (such as knobs or keyboards) can be inoperative.

Lockout (LOK) Signal
The LOK pin asserts when the LOK bit asserts. The LOK bit is ISR2[5] in 7210 mode. The LOK bit is ADSR[6] in 9914 mode. LOK asserts when the NAT4882 GPIB RL function is in either Local With Lockout State (LWLS) or Remote With Lockout State (RWLS).

When LOK asserts, the IEEE 488 Return To Local (rtl) message is disabled. Refer to the rtl auxiliary command in the AUXMR and AUXCR descriptions.

My Address (MA) Signal
The MA signal pulses when the NAT4882 receives its primary talk or listen address from the Active Controller.

Referring to the IEEE 488.1 specification: MA = DAV & (MTA + MLA)

DMA Pins If DMA Operation Is Not Required

DRQ
DRQ is an output-only pin. If the application does not require direct memory access (DMA), you can leave DRQ unconnected.

DACK*
The DACK* pin is an active low input-only pin with an internal pull-up resistor. If the application does not require DMA, you can connect DACK* to Vcc or leave DACK* unconnected.

TC
The TC pin is an active high input-only signal. If the application does not require DMA, you should connect TC to ground (GND).

PAGE-IN Pin

7210 Mode Registers
In 7210 mode, the NAT4882 is software compatible with the NEC mPD7210. The mPD7210 has three address pins and requires eight bytes of address space.

The NAT4882 has several registers not implemented in the mPD7210. These registers are called page-in registers. The host interface can access the page-in registers in one of two ways: by using the PAGE-IN pin or by using the page-in auxiliary command.

The PAGE-IN pin has no effect in 9914 mode.

Using the PAGE-IN Pin
If the PAGE-IN pin is asserted, the application program can access the page-in registers. If the PAGE-IN pin is connected to an additional I/O address signal, the page-in registers always appear in the I/O address space.

For example, suppose that you connect address signal 3 (ADDR[3]) of the CPU to the PAGE-IN pin and connect the ADDR[2:0] signals of the CPU to the NAT4882 A[2:0] pins. Table 1 represents the NAT4882 address map. Notice that the PAGE-IN pin does not affect some registers; these registers appear twice in the address map.



Using the Page-In Command
If possible, you should use the PAGE-IN pin as described in the previous section, Using the PAGE-IN Pin. If your application does not have sufficient address space to use the PAGE-IN pin, connect the PAGE-IN pin to GND.

If the PAGE-IN pin is connected to GND, you must use the page-in auxiliary command to access page-in registers. Write the page-in command to the AUXMR before you access a page-in register. In 7210 mode (unlike 9914 mode page-in registers), any chip access (including a DMA access) clears the page-in auxiliary command. Thus, you should disable DMA when you access a page-in register with the page-in command.

ACCEN Pin
The ACCEN pin is used only in 9914 mode. ACCEN is an output-only pin that asserts when any page-in register appears at offset 2. In most applications, you can leave this pin unconnected.

In 9914 mode, the NAT4882 is software compatible with the TMS9914A. The TMS9914A has three address pins and occupies eight bytes of address space. However, no writable register appears at offset 2 in the TMS9914A, and no readable register appears at either offset 4 or 5. You can map external registers to these unused offsets in the 9914 address space. Alternatively, you can program the NAT4882 to map internal registers to these offsets.

The NAT4882 has several registers not implemented in the TMS9914A. These registers are called page-in registers.

You can page-in four different writable registers at offset 2. Four auxiliary commands correspond to the four registers that can appear at offset 2. In 9914 mode (unlike 7210 mode), a register remains paged-in until you page-in a different register or until you write the Clear Page-In Registers (clrpi) command to the AUXCR.

When any register is paged-in at offset 2, the ISR2 readable register appears at offset 4 and the SPSR readable register appears at offset 5. The ACCEN pin asserts when any register is paged-in at offset 2.

GPIB Signal Pins
You can directly connect the NAT4882 GPIB signal pins to a GPIB transceiver. One popular transceiver is the 75162 IC. If you use a 75162, you must connect the GPIB bus pins on the 75162 (usually pins 2 through 9 in a DIP package) to the GPIB connector and connect the terminal pins (pins 12 through 19 in a DIP package) to the NAT4882.

Key Pins
The key pins (KEYRST*, KEYDQ, and KEYCLK*) are designed to be directly connected to a Dallas Semiconductor DS1204U Electronic Key. The application software can check for the presence of a security key.

Applications that do not use the key can leave the key pins unconnected. You can also use the Key Reset (KEYRST*) bit, Key Data (KEYDQ) bit, and Key Clock (KEYCLK*) bit pins as general-purpose, TTL, digital I/O pins.

Test Pins
You must leave the TESTOUT pin unconnected. You must connect the TESTIN pin to GND.
Related Links:
NAT4882 Programmer Reference Manual

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