Emulating an LVDT with the NI PXI-78xxR RIO Device

This tutorial describes the example code for emulating a Linear Variable Differential Transformer (LVDT) sensor for HIL and other test applications using LabVIEW FPGA and the NI 78xxR RIO boards.

Background and Scope

Engineers who design and test electronic modules that control aircraft, automobiles, and other systems often perform hardware in the loop (HIL) testing for validation and verification test.

One of the key elements of an HIL test system is the ability to emulate the sensor signals connected to the electronic module when it is deployed.  By simulating environmental conditions at the sensor inputs, the testing process can verify the behavior of the control module under a wide variety of  operating conditions, including conditions that would not be tested safely in the real world.

Figure 1.  Sensor Emulation for HIL Application

A Linear Variable Differential Transformer (LVDT) is a sensor that uses a differential transformer with a sliding magnetic core to sense displacement.  LVDTs are driven by an AC excitation source, typically a sine wave in the 2.5 to 3.5 kHz range, and generate an AC output signal that is proportional to the mechanical position of the core. 

The output signals can be processed to recover the displacement value.  Some LVDTs (referred to as DC LVDTs or DCDTs) have built-in excitation and demodulation circuitry that provides a DC output signal, but in most control applications the controller provides the excitation voltage and processes the raw LVDT output signals.

Emulating an LVDT takes some effort because the output signals are AC waveforms that are proportional to and in phase with the excitation signal provided by the controller. Traditional LVDT emulation approaches include:

• Using a motion control system to position the core of a physical LVDT sensor.
• Using a DSP processor and analog I/O circuitry to measure the excitation signal and synthesize the output signals.

LV FPGA can emulate LVDT signals with the performance and flexibility of a DSP processor without the complexity and development cost of an embedded DSP design.

The FPGA-based LVDT Emulator

Note:  The following example is compatible with RIO boards that have analog inputs and outputs (783xR and 785xR).  It does not work with all-digital devices such as the 781xR series boards.

This example acquires the LVDT excitation signal and calculates the corresponding output to emulate the LVDT displacement position. The output value is the product

V_o =  simulated sensitivity * simulated displacement * latest excitation voltage measurement 

Sensitivity is a constant value (specified in V/V/mm), and is a calibration constant for the specific LVDT to be emulated. 

Note that the latency between the excitation measurement and output update introduces a small phase delay between the excitation and emulated signals.  

Hardware Considerations
This example uses a single analog output to emulate an LVDT with a single output winding.  To emulate an LVDT with a center-tap output, this example can be modified to use two analog outputs.

NI 78xxR devices have 8 analog inputs and 8 analog outputs, so they can emulate up to 8 single-winding LVDTs or 4 center-tapped LVDTs. The following block diagrams only show one LVDT channel (single winding) for clarity.

The excitation voltage is connected to one of the analog inputs, and the output voltage is generated on the corresponding analog output. The analog inputs and outputs operate up to ± 10 V (7 V_rms).

Software Considerations
A example is divided into two parts: the FPGA VI and the host VI. The host VI, running on either Windows or a Real-Time target, performs a few floating point calculations and provides an API for rest of the application.  The FPGA VI (shown below) runs on the NI 78xxR and provides the instantaneous output response to rapid changes in the excitation signal. 

LabVIEW FPGA does not support floating-point operations, so the output value calculation is done in two steps (see Figure 2). First, the excitation measurement (16-bit integer) value is multiplied by a 32-bit scaling factor. The resulting value is bit-shifted to form the output (16-bit integer) value. The combination of  multiplication and bit shifting provides the desired scaling factor.   As you will see, the bit-shifting compensates for a multiplying factor applied to the scaling factor on the host VI.  Without getting into the details, this process provides the dynamic range within the integer math domain to support the flexibility and accuracy needed for most applications.

The emulation algorithm is pipelined so that input and output (the performance limiting operations) can be performed in parallel.  Note that the loop rate is dominated by the slower of the two operations and the total latency from input to output is the update period + the AO operation delay.

The host VI calculates and updates the scaling factor as the simulated displacement value changes. The scaling factor is the product of 

SF = sensitivity * position * a scaling constant

The scaling constant in this example is 16384, or 2¹⁴, which corresponds to the negative 14-bit shift performed by the FPGA VI.

Figure 3. Scaling Factor Calculation in the Host VI

The example shown in the preceding diagrams uses a 14-bit logical shift in the FPGA VI and a scaling constant of 16384 in the host VI, which works for emulated LVDTs with a full-scale output-to-excitation ratio up to 2x, according to the table in Figure 3.

To calculate the full-scale output range and output ratio for a particular LVDT, use the following equations:

The full-scale output calculation is important for verifying that the output signal does not exceed the 7Vrms compliance range of the NI 78xxR analog outputs.

The full-scale output ratio is the following:

So to emulate this LVDT, use a bit shift of -15 and a scaling constant of 32768.

Host VI Example
The figure below shows a simple example of using the LVDT emulator in a host application. The LVDT emulator is controlled from a LabVIEW or LabVIEW Real-Time application by starting the FPGA VI, initializing the LVDT position and sensitivity variables, and updating the simulated position as needed during the test (shown here within a loop).

Performance Characteristics

Download the Example Code

The example code can be downloaded here.

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