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Document Type: Tutorial
NI Supported: Yes
Publish Date: Sep 6, 2006

Features Supported by NI 5102/5620/5621/5911 High-Speed Digitizers

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Return to Fundamentals of High-Speed Digitizers

For features of other National Instruments High-Speed Digitizers see Features Supported by NI 5112/5114/5122/5124/5922 High-Speed Digitizers

Input Configuration

Maximum Input Range
±5 V
±1 V (±10 dBm)
±1 V (±10 dBm)
±10 V
DC Offset
N
N
N
N
Input Impedance
1 MΩ,
50 Ω
50 Ω
50 Ω
1 MΩ
Input Coupling
AC, DC
AC only
DC only
AC, DC
3 dB Bandwidth
0 MHz to 15 MHz
10 kHz to 36 MHz
0 MHz to 36 MHz
0 MHz to (0.4 x sample rate);
6 MHz max
Timing
Maximum Real-Time Sample Rate
20 MS/s
64 MS/s
64 MS/s
100 MS/s
Maximum RIS Sample Rate
1 GS/s
1 GS/s
Time Stamps
Relative
Absolute, Relative
Absolute, Relative
Relative
Triggering
Reference (Stop) Trigger Types
Immediate, Analog Edge, Digital Edge, Hysteresis, Window
Immediate, Digital Edge, Software, Analog Edge, Analog Window, Analog Hysteresis
Immediate, Analog Edge, Digital Edge, Hysteresis, Window, Software
Immediate, Analog Edge, Digital Edge, Hysteresis, Window, Software
Reference (Stop) Trigger Sources
CH 0,
CH 1,
TRIG,
PFI<1..2>,
RTSI<0..6>,
PXI STAR
PFI 1,
RTSI<0..6>,
PXI STAR
CH 0,
PFI<1..2>,
RTSI<0..6>
CH 0,
PFI<1..2>,
RTSI<0..6>
Trigger Coupling (External TRIG Input)
AC, DC
Trigger Coupling (Analog Input Channel)
Same as input channel
Same as input channel
Same as input channel
Same as input channel
Trigger Holdoff
From end of acquisition to trigger
From trigger to first point of next record
Trigger Delay
N
N
N
N
External TRIG Input Impedance
1 MΩ
Clocking
Reference Clock Input Sources
PFI<1..2>,
RTSI Clock (RTSI 7)
REF CLK IN,
PXI CLK 10
REF CLK IN,
PXI CLK 10
PFI<1..2>,
RTSI Clock (RTSI 7)
Reference Clock Frequency
20 MHz
10 MHz
10 MHz
10 MHz
Reference Clock Outputs
PFI<1..2>,
RTSI Clock (RTSI 7)
PFI<1..2>,
RTSI Clock (RTSI 7)
PCI Internal Reference Clock Outputs
PFI<1..2>,
RTSI Clock (RTSI 7)
PFI<1..2>,
RTSI Clock (RTSI 7)
External Sample Clock Sources
PFI<1..2>,
RTSI<0..6>
External Sample Clock Frequency
1 kHz to 20 MHz
Sample Clock Outputs
PFI<1..2>,
RTSI<0..6>
Acquisition
Acquisition Modes
Normal
Normal, DDC
Normal, DDC
Normal, Flex Res
Multiple Records
N
Y
Y
Y
Continuous Acquisition
N
Y
Y
N
Synchronization Triggers
Arm Reference Trigger Sources
Record Advance Trigger Sources
Record Arm Trigger Sources
Start Trigger (Acquisition Arm) Sources
PFI<1..2>,
RTSI<0..6>,
PXI STAR
Reference (Stop) Trigger Outputs
PFI<1..2>,
RTSI<0..6>
PFI 1,
RTSI<0..6>
PFI 1,
RTSI<0..6>
PFI<1..2>,
RTSI<0..6>
End of Record Outputs
End of Acquisition Outputs
Start Trigger Outputs
PFI<1..2>,
RTSI<0..6>
Master–Slave Trigger Delay Correction
N
N
N
N
Miscellaneous
Self-Calibration
RIS Timing Only
N
N
Y
Probe Compensation
PFI 1 (1 kHz)
LabVIEW Real-Time Support
N
N
N
N
Memory per Channel
663,000
16 or 32 MS (not using DDC),
8 or 16 MS (using DDC)
32 MS (not using DDC),
16 MS (using DDC)
4 or 16 MB
Sample Width
8 bits
16 bits
16 bits
32 bits


Related Links:
Fundamentals of High-Speed Digitizers
Features Supported by High-Speed Digitizers

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