Linearity of Analog-to-Digital Converter (ADC)
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In selecting a digital-to-analog converter (DAC) one of the most common criteria you look at is linearity. Two tests have evolved as the most popular linearity tests: differential nonlinearity (DNL) and integral nonlinearity (INL.) If an ADC were ideal, each output step would be exactly the same size; when supplied with equally increasing increments of supply voltage, the output would ramp up in equal increments. DNL is the degree to which each output step (or code width) varies from the ideal step. INL measures the deviation of the entire transfer function from the ideal function.
To test the linearity of an ADC, you need to generate the analog stimulus and capture the digital response. Usually you would sweep the ADC from its minimum to maximum input, and compare the response to what it should be at every output code width. When most manufacturers specify DNL and INL on a data sheet, they specify the worst cases - the maximum and minimum over the entire transfer functions. You might only be interested in the minimum and maximum, or you might be interested in the measurements for all code widths. LabVIEW provides native array functions to search the data array for the max and min or other points of interest, and you can graph the overall transfer functions for trending information.
To generate the analog stimulus and capture the digital response, you need a high-speed source and a high-speed digital device. In hardware, you need to control the timing between the acquisition and generation modules, so you know which acquisition sample should correspond to which generation sample. Platforms such as PXI and VXI are ideal for such applications. These platforms are designed with timing and synchronization resources built-in, so modules can share reference clocks, sample clocks, triggers, and events.
Figure 1. Differential Nonlinearity of ADC
Related Links:
Mixed-Signal Stimulus-Response
Linearity of Digital-to-Analog Converter (DAC)
ADC Linearity Test
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