Menu Changes Between the FPGA Module 1.1 and the FPGA Module 8.0

The table below explains how to perform actions using the FPGA 1.1 Module compared to using the FPGA 8.0 module. LabVIEW FPGA 1.1 makes use of the Embedded Project Manager (EPM) and creates LabVIEW Embedded Project (.lep) files. The LabVIEW FPGA 8.0 module uses the LabVIEW Project Explorer Window (Project) and creates LabVIEW Project (.lvproj) files.

Action	FPGA 1.1	FPGA 8.0
Target an FPGA device	Switch Execution Target from the LabVIEW Startup Window	Add an FPGA Target to a Project
Target an FPGA emulator	Switch Execution Target from the LabVIEW Startup Window	Project>FPGA Target (right-click)>Properties>General
Saving Project with different name	EPM>>FILE>>Save Project As	Create new Project and copy items
Save Distribution	EPM>>FILE>>Save Project with Options	Use Build Specifications in Project
Import from other project	EPM>>Project>>Import	Copy and paste between Projects
Force a compile	EPM>>Target>>Build (or build button in EPM or CTRL-Run arrow in VI)	Project>FPGA Target>VI (right-click)>Compile (or CTRL-Run arrow in VI)
Designate Build Clock Rate for VI	EPM>>Target>>Build (or build button in EPM)	Project>FPGA Target (right-click)>Properties>Top-Level Clock
Set Auto Run VI on load for VI	EPM>>Target>>Build (or build button in EPM)	Project>FPGA Target (right-click)>Properties>General
Download VI to FPGA	EPM>>Target>>Download	Project>FPGA Target>VI (right-click)>Download
Run VI on FPGA	EPM>>Target>>Run (or run button in EPM or VI)	Project>FPGA Target>VI (right-click)>Run or Run arrow in VI
Set Client Compile Server directory	EPM>>Target>>Build Options	Tools>>FPGA Module Options>>Configure
Set Compile Server Machine, port, timeout	EPM>>Target>>Build Options	Tools>>FPGA Module Options>>Configure
Set Default Build Clock Rate for System	EPM>>Target>>Build Options	N/A
Set Default Auto Run VI on load for System	EPM>>Target>>Build Options	N/A
Manage FPGA I/O items	EPM>>Hardware>>Alias Manager	Use the Project to create and edit FPGA I/O
Manage cRIO modules	EPM>>Hardware>>Configure Target for CompactRIO	Use the Project to create and manage C Series Modules
Put VI on FPGA Flash Memory	EPM>>Tools>>Download VI or Attributes to Flash Memory	Project>FPGA Target>VI (right-click)>Download VI or Attributes to Flash Memory…
Set Auto Load from Flash behavior	EPM>>Tools>>Download VI or Attributes to Flash Memory	Project>FPGA Target>VI (right-click)>Download VI or Attributes to Flash Memory…
Set Analog Input Mode (Diff, RSE, NRSE)	EPM>>Tools>>Download VI or Attributes to Flash Memory	Project>FPGA Target>VI (right-click)>Download VI or Attributes to Flash Memory…
Synchronize FPGA Clock to PXI_CLK10	EPM>>Tools>>Download VI or Attributes to Flash Memory	Project>FPGA Target>VI (right-click)>Download VI or Attributes to Flash Memory…
Reset Board	N/A	Project>FPGA Target>VI (right-click)>Reset
Configure Dialogs	LabVIEW INI File	Tools>>FPGA Module Options

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