Using the NI 655x for Logic Analyzer Applications

During the process of debugging and validating a digital system, a common task is the acquisition of digital waveforms. A logic analyzer is a tool that allows numerous digital waveforms to be acquired simultaneously. The acquisition can be clocked internally, or the System Under Test (SUT) can provide the sample clock. A logic analyzer also supports multiple triggering schemes to determine when data is acquired.

The NI 655x has many features that make it ideal for digital waveform acquisitions. These include flexible memory sizes, voltage levels, and input impedances, advanced acquisition timing options, diverse acquisition triggering choices, powerful data visualization programming features, and extensive expansion and integration capabilities.

Flexible Memory Sizes, Voltage Levels, and Input Impedances

When performing a digital waveform acquisition, it is frequently a requirement to acquire data from multiple channels. In many situations, the signals of interest are a bus of data or control lines. The NI 655x provides 20 data channels that can be used for simultaneous digital waveform acquisitions. Each of these channels has a deep on board memory used to store data during acquisitions. Three memory sizes are available with the NI 655x to suit a wide range of applications: 1 Mbit per channel, 8 Mbits per channel, or 16 Mbits per channel.

The NI 655x provides further flexibility by allowing the user to set custom voltage levels. These levels are adjustable in 10 mV increments from -2 V to +5.5 V. This range allows compatibility with common logic families such as CMOS, TTL, and LVTTL, as well as nonstandard logic levels. Additionally, the data channels have a programmable input impedance of 50 W or high-impedance (10 kW). All of the channels share the selected voltage levels and input impedance.

Advanced Acquisition Timing Options

The rate at which digital data is being transferred is ever increasing. This creates the need for high-speed digital waveform acquisitions. The NI 655x meets this need by supporting sample clock rates of up to 100 MHz with the NI 6552 and 50 MHz with the NI 6551. In addition to high sample clock rates, precise control over when data is acquired during a sample clock period is also extremely important. Digital waveform acquisitions with the NI 655x are controlled by two clocks: the sample clock and the reference clock.

The sample clock is the primary timebase for a digital waveform acquisition. This clock controls when samples are acquired. Each period of the sample clock is capable of initiating the acquisition of one sample per channel. The NI 655x is capable of acquiring data at different positions relative to the pulses of the sample clock. These positions include rising edge data, falling edge data, and delayed data. Delayed data is acquired at a specified time after the rising edge of the sample clock. The delay can vary between 0 and 100% of the clock period with a resolution of 0.4% of the clock period. Figure 1 illustrates the three available data positions.


The sample clock can be programmed to come from either the on board clock source or an external clock source. The on board clock source is a high-precision 200 MHz Voltage Controlled Crystal Oscillator (VCXO) clock source. To generate the sample clock, the NI 655x can divide the on board clock source by any integer from 2 to 4,194,304 for the NI 6552 and from 4 to 4,194,304 for the NI 6551. An external, free-running clock frequency can be provided as the sample clock rate through an SMB jack connector on the NI 655x front panel or the PXI backplane. The STROBE channel, a dedicated channel for an external sample clock on the Digital Data & Control (DDC) VHDCI connector, should be used for applications where source-synchronous data transfer is required. The data and sample clock travel together through the cable from the SUT to the NI 655x.

To guarantee a high level of precision, the on board clock source can use a phase locked loop (PLL) circuit to lock the internal timebase of the NI 655x to a known reference frequency. This is the reference clock. The most common source is the 10 MHz reference clock available from the PXI backplane. A reference clock for the PLL can also be provided through an SMB jack connector on the NI 655x front panel.

In addition to using external clocks for digital waveform acquisitions, it is often necessary to export either the sample or reference clock to the SUT. The NI 655x has the capability to export its sample clock to the DDC connector or an SMB jack connector on the NI 655x front panel. If a reference clock for the PLL has been configured, it can also be exported to an SMB jack connector on the NI 655x front panel.

Diverse Acquisition Triggering Choices

As well as advanced acquisition timing options, it is crucial to posses the ability to control, or trigger, a digital waveform acquisition based on a variety of digital events. The NI 655x supports numerous trigger types. A common digital event is the transition of a signal from low to high (rising edge) or high to low (falling edge). These are known as edge triggers. The second trigger type, a pattern match trigger, configures the NI 655x to monitor the input channels for a specific pattern (i.e. '10100111'). When this pattern is detected on the input channels, the trigger asserts. A pattern match trigger can also be configured to trigger the NI 655x when the pattern is not matched. Moreover, a trigger can be configured for a signal transition below the defined low level or above the defined high level. Triggers based on these digital events are known as level triggers. Finally, the NI 655x supports a software trigger, which is generated internally by a programmatic call in software.

The NI 655x also supports various actions that a trigger can initiate. In many situations, it is desirable to acquire a certain number of samples of digital data before (pretrigger) and after (posttrigger) a trigger. A reference trigger establishes the reference point that separates pretrigger and posttrigger samples. A start trigger, on the other hand, simply starts the process of sampling and storing data. The supported types for a reference trigger and a start trigger are edge, pattern match, and software. Furthermore, during an active digital waveform acquisition, the ability to pause the sampling can be quite useful. A pause trigger accomplishes this task. The supported types for a pause trigger are level and pattern match.

Powerful Visualization Programming Features

The NI 655x can be programmed in LabVIEW 7 Express (or later), LabWindows/CVI 6.0 (or later), or C/C++. The fact that the NI 655x is programmable gives the user extensive control over its functionality. This flexibility leads to applications that are completely customizable. To assist with development, example programs demonstrating the major features of the NI 655x are available for each of the supported programming languages.

Often, digital data must be displayed on a user interface. LabVIEW includes the Digital Waveform Graph, a powerful user interface object that allows digital data to be displayed in a very informative and logical manner. Figure 2 is an example of a Digital Waveform Graph.


In addition to displaying single channels of digital data, multiple channels can be grouped together and displayed as buses. The format of the bus plots can be hexadecimal, decimal, octal, or binary. Figure 3 is an example of a Digital Waveform Graph displaying two buses of hexadecimal digital data.


LabVIEW also provides the Digital Table. This user interface object allows digital data to be displayed as text. The format of the text can be hexadecimal, decimal, octal, or binary. Figure 4 is an example of a Digital Table containing binary digital data.

Some applications require more than the 20 digital waveform acquisition channels provided by a single NI 655x. In these situations, the integrated timing and triggering capabilities of the PXI form factor makes it simple to synchronize multiple NI 655x devices in a system. PXI chassis are available with 4, 8, or 18 slots. Once multiple NI 655x devices have been added to a system to reach the desired channel count, synchronization of these modules is straightforward. For additional information concerning the synchronization capabilities of the NI 655x, please refer to the NI Digital Waveform Generator/Analyzer Help or contact a National Instruments Applications Engineer.

Besides performing digital waveform acquisitions, the NI 655x is also capable of generating digital waveforms. In fact the NI 655x can acquire and generate simultaneously. During the process of debugging and validating a digital system, the ability to output digital data is often necessary to control an SUT or simulate input data. As with acquisitions, for digital waveform generations the NI 655x supports sample clock rates up to 100 MHz with the NI 6552 and 50 MHz with the NI 6551.

Complex triggering schemes involving a sequence of trigger events may be desired in certain situations. With the LabVIEW FPGA Module and NI PXI-7831R User-Configurable I/O Hardware, the ability to trigger the NI 655x based on a user-defined sequence of trigger events is achievable. For example, it would be possible to trigger an NI 655x after the data bus on an SUT matches a certain pattern, but only if another pattern is matched on the data bus within a given amount of time. With the combination of the NI 655x and the NI 7831R, countless complex triggering schemes become a reality.

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