Using the TNT4882 in an MC68340 System

This application note is written for GPIB instrument designers who use the Motorola MC68340 processor. It describes the hardware interface required to create a fully functional GPIB device using the National Instruments TNT4882 GPIB interface chip with the Motorola MC68340.

Introduction

In this document we show how to create an interface that will meet the following specifications:

• Complete IEEE 488.2 Talker/Listener functionality based on the TNT4882-AQ
• 8 and 16-bit data transfers
• Polled I/O, Interrupt Driven I/O, and Direct Memory Access (DMA)
• 16-bit Single Address DMA transfers between RAM and TNT4882

Note that the terms assert (assertion) and negate (negation) are used to avoid confusion when dealing with a mixture of active low and active high signals. The term assert (assertion) means that a signal is active or true, independent of the level represented by a high or low voltage. The term negate (negation) means that a signal is inactive or false, independent of the level represented by a high or low voltage.

Source files for the test program are included in the Appendix. Before you use the hardware test program, make any changes necessary to the header files and recompile the program. We used Microtec Research Software Development Tools, Version 4.2D for DOS and an M6834OEVS System.

Hardware Description

The TNT4882 has two different pin configurations – ISA and Generic. This application uses the TNT4882 in Generic pin configuration. Refer to Chapter 5 in the TNT4882 Programmer Reference Manual for a Generic pin description. Figure 1 shows the MC68340 and TNT4882 hardware interface diagram. The interface logic can be implemented easily in a Programmable Array Logic (PAL) device such as a 16V8.


Synchronous Bus Operation

TNT4882 Address Lines
Address lines A6-A2 of MC68340 connect directly to the address lines of TNT4882. Although TNT4882 only requires 32 bytes of address space a total of 256 bytes are assigned. To take advantage of the longword instructions in MC68340, TNT4882 FIFOs must be aligned on a word boundary. For this reason the A6-A2 lines of MC68340 are connected to A4-A0 lines of the TNT4882 chip. Thus every TNT4882 register is assigned to four consecutive address location for a total of 256 bytes.

TNT4882 Data Lines
Since the TNT4882 has built-in transceivers, the data lines connect directly to the CPU without requiring any external pull-up resistors. All TNT4882 registers require 8-bit transfers except FIFO B that allows both 8-bit and 16 bit data transfers. 8-bit I/O accesses can use either data bus. The selection of the data bus is controlled by the ABUSN and BBUSN signals. The only allowed 16-bit accesses are reads and writes to FIFO B. ABUSN and BBUSN must both be asserted during 16-bit I/O accesses.

TNT4882 ABUSN, BBUSN Signals
The TNT4882 has the capability of using either of its data busses for 8-bit I/O accesses. Either Bus A (D15-8) or Bus B (D7-0) can be selected using the ABUSN and BBUSN signals. These two signals can be controlled by using SIZ0 and A0 signals of the processor. Whenever accesses are made to an odd byte address, the processor uses the lower byte of the data bus and whenever accesses are made to an even byte address, the processor uses the upper byte of the data bus. Table 1 shows the ABUSN and BBUSN signals with respect to SIZ0 and A0.



Figures 2 and 3 show the CPU read and write timing diagrams, respectively.




TNT4882 RDN, WRN Signals
During write accesses, the TNT4882 latches data on the rising edge of WRN. The TNT4882 drives its data buses when RDN is asserted during read accesses. The processor asserts DSN to indicate that an external device should place valid data on the bus during a read access, and that valid data is on the data bus during a write access. The R/W signal indicates the direction of data transfer on the bus. When Direct Memory Access (DMA) is used, DACKN is asserted by the CPU to indicate that a word is being transferred. Since we are implementing single address DMA, DACKN and R/W signals should be used to control RDN and WRN during DMA accesses. Table 2 shows the RDN and WRN signals with respect to R/W, DSN, DACKN.



TNT4882 DMA Signals

The processor has a built-in DMA controller so our system does not require an external DMA controller. The system supports 16-bit Single Address DMA transfers between system memory and the TNT4882 FIFOs. Only one DMA channel is used. Since MC68340 will start DMA when DREQN1 is asserted, the DRQ signal of the TNT4882 must be inverted and then connected to the DREQN1 pin of MC68340. The DACKN signal from the TNT4882 can be connected directly to the DACKN1 pin of MC68340. Figures 4 and 5 show the DMA read and write cycles respectively.


Asynchronous Bus Operation
Normally, the TNT4882 is used in one chip mode. See Chapter 2 in the TNT4882 Programmer Reference Manual. To maintain backwards compatibility, the TNT4882 can be used in two chip mode. In the two chip mode, the TNT4882 duplicates the Turbo488/NAT4882 chipset. In two chip mode the processor can access registers in both the Turbo488 and NAT4882 but all NAT4882 accesses have to pass through the Turbo488, hence they take a little longer time. To accommodate for this feature, one can use the asynchronous timing of MC68340 processor. Asynchronous timing on MC68340 can be controlled by using the DSACKNx pins. The TNT4882 provides two signals namely RDY1 and CPUACC which can allow the user to handle delays in I/O accesses.

The TNT4882 asserts CPUACC to indicate the processor to lengthen the current I/O access. RDY1 indicates that the TNT4882 is ready for the host interface to complete the lengthened cycle if CPUACC is asserted. If CPUACC is not asserted, RDY1 indicates that the current I/O cycle does not need to be lengthened, it does not indicate that the current cycle has finished. Therefore, DSACKN1 should be negated when CPUACC is asserted and RDY1 is negated. See Chapter 5 in the TNT4882 Programmer Reference Manual.



Interrupt Acknowledge Bus Operation
The TNT4882 can interrupt the processor by asserting its interrupt signal. The MC68340 will acknowledge the interrupt if its priority is higher than the interrupt mask in the status register. For the above example, interrupt level three has been selected. Since the TNT4882 cannot supply a vector number, it requests an automatically generated vector (autovector). Instead of placing the vector number on the data bus, the autovector register is programmed to generate an autovector. The DSACKNx signals of MC68340 must be negated during the interrupt acknowledge cycle so that the autovector is generated internally. Therefore, DSACKN1 should also be negated when the TNT4882 INTR is asserted. Table 3 shows the DSACKN1 control signals:


Other CPU Interface Pins¹

Chip Select (CSN)
The CSN pin of the TNT4882 can be connected to one of the available chip select pins of the processor. This allows the chip select to be controlled in software which provides us with some flexibility in moving the TNT4882 anywhere in MC68340 memory map.

Reset (RESETN)
The RESETN pin of the TNT4882 can be connected directly to the RESETN pin of MC68340. Asserting the RESETN signal will reset the TNT4882.

Interrupt Signal (INTR)
MC68340 IRQ lines are active low, so the INTR signal from the TNT4882 must be inverted and then connected to one of the available interrupt lines.

PAGED Pin
When the PAGED pin on the TNT4882 is asserted, the TNT4882 enters the Paged-In state. If Page-In state is true, several registers are mapped to different offsets. In all new applications, PAGED may be connected to GND.

MODE Pin
The MODE pin determines whether the TNT4882 enters Turbo+7210 mode or Turbo+9914 mode after a hardware reset. For the above interface, MODE was left unconnected so that the TNT4882 enters the Turbo+7210 mode. See the MODE & SWAPN Pin Recommendations section of the TNT4882 Programmer Reference Manual.

SWAPN Pin
The TNT4882 samples the SWAPN pin during a hardware reset. If SWAPN is asserted during a hardware reset, the SWAP bit is set. For the above interface, SWAPN pin was left unconnected. See the MODE & SWAPN Pin Recommendations section of the TNT4882 Programmer Reference Manual.

FIFO_RDY Pin
The FIFO_RDY output indicates that the FIFOs are ready for at least 8 word (or byte) transfers. Since we did not have any use for FIFO_RDY, it was left unconnected.

ABUS_OEN and BBUS_OEN
The ABUS_OEN output asserts when the TNT4882 drives Data Bus A during a read access. The BBUS_OEN output asserts when the TNT4882 drives Data Bus B during a read access. Since we did not have any use for the above pins, they were left unconnected.

BURST_RDN
When BURST_RDN is asserted, the TNT4882C drives Data Bus A and Data Bus B with the next word to be read from the FIFOs. BURST_RDN does not remove data from the FIFOs. For the above interface, BURST_RDN was left unconnected.

Key Pins (KEYRSTN, KEYDQ, KEYCLKN)
The key pins are designed to be connected to a Dallas Semiconductor DS1204U Electronic Key. Applications that do not use the key can leave the key pins unconnected.

GPIB Device Status Pins
The TNT4882 has five device status pins: TADCS, LADCS, TRIG, DCAS, and REM. All device status pins are output only so we left them unconnected. For further description of the status pins, refer to the TNT4882 Programmer Reference Manual.

GPIB Signal Pins
Connect the GPIB signal pins directly to a GPIB connector.

Oscillator Pins (XTALI, XTALO)
A 40-MHz oscillator is required to drive the clock signal. Connect the oscillator output to the XTALI pin of the TNT4882; leave the XTALO pin unconnected.

Vcc and GND Pins
Supply power to all the Vcc pins and connect the ground signal to all the GND pins.


¹ For a detailed description, please refer to Chapter 5 of the TNT4882 Programmer Reference Manual.

See Also:
TNT4882 Programmer Reference Manual

Software Consideration

Once the hardware interface has been constructed, a few initialization routines need to be performed. Once these initialization sequences are complete, the CPU can be programmed to implement any GPIB device.

System Configuration
System configuration must be performed before the TNT4882 can be used. Configuration of the system requires you to initialize and configure the System Integration Module (SIM), the interrupt registers, and the DMA channel. Once you have configured these modules, the MC68340-TNT4882 interface is fully functional.

System Integration Module Configuration
Configure the appropriate chip select registers in the SIM so that the TNT4882 can be selected. With the above setup, 256 bytes are required. Therefore, CSN2 registers are configured and the TNT4882 is located at $00FFE800 in MC68340 address space. Table 4 shows the register map of the TNT4882 in MC68340 address space. As you can see, every register in the TNT4882 can be accessed by four different addresses. This setup allows you to use longword accesses from the FIFOs and gives you the choice of using either the upper byte lane or the lower byte lane.



Interrupt Configuration
Since the above setup requires an autovector, we need to program the autovector register so that the vector number is generated internally when an interrupt is acknowledged. In the above case, we are using interrupt level three, therefore $08 should be stored in the autovector register.

The vector table should also be modified to point to the new interrupt handler. For interrupt level three, the vector is stored at location $06C. The value contained at this memory location should be modified to contain the address of the new interrupt handler.

DMA Channel Configuration
In order to use DMA, the DMA channel must be configured for single address, burst mode, and external request generation. On GPIB reads, the TNT4882 will assert its DRQ signal if the FIFOs contain a byte that needs to be transferred to memory. On GPIB writes, the TNT4882 will assert its DRQ signal when the FIFOs are not full.

For every system there is a point where programmed I/O is faster than DMA I/O and vice versa. Programmed I/O is usually faster for small transfer sizes (500 bytes or less). It is recommended that you determine the crossover point and then use it as a switch to decide when to use programmed I/O or DMA.

Device Level Programs
We recommend using the TNT4882 in one-chip mode. The TNT4882 by default powers up in two-chip mode to maintain backwards compatibility. Therefore, it is important to initialize the TNT4882 so that it is in one-chip mode. Follow the steps listed in the ESP-488TL Software Reference Manual for TNT4882. The manual also includes sample routines that can help you write programs for the TNT4882.

See Also:
ESP-488TL Software Reference Manual for TNT4882

Hardware Interface Test

A hardware interface test and library is included with this package. Before you use the hardware test, make any changes if necessary to the header files and re-compile the program. We used Microtec Research Software Development Tools, version 4.2D for DOS and an M68340EVS System. The header files include information such as the base address where the TNT4882 is located. The hardware interface test program tests the interface between MC68340 and TNT4882. It performs three different types of I/O:

• Programmed I/O
• Interrupt Driven I/O
• DMA I/O

To perform the hardware test, download the HARDWARE.ABS file on the MC68340EVS system. The HARD-WARE.ABS file is in the HARDWARE directory.

Downloading Procedures
A Widows terminal settings file is also included on the disk. Execute the following steps to download a program:

1. Start Windows.
2. Choose RUN from the FILE menu.
3. Type A:\MC68340.TRM to start the Windows Terminal program.
4. Type LO and press <ENTER>.
5. Choose Send Text File from the Transfers menu.
6. Select HARDWARE.ABS from A:\HARDWARE directory.
7. When download has completed, hit <ENTER> twice.

Once the program has been downloaded, use the RM command to initialize the MC68340 registers. Set PC to $4000, USP to $8000 and SSP to $10000.

Programmed I/O Test
In Programmed I/O, 5 different tests are conducted that make accesses to FIFOs. These five tests are:

1. 8 Bit Accesses to FIFO A
2. 8 Bit Accesses to FIFO B
3. 16 Bit Accesses to FIFOs
4. 8 Bit Writes and 16 Bit Reads
5. 16 Bit Writes and 8 Bit Reads

Programmed I/O tests 1 and 2 write all possible values (0-255) to both the FIFOs using the upper byte lane and the lower byte lane. Test 3 makes 16-bit accesses to the FIFOs by writing specific values which test the address and data lines (stuck-0,stuck-1,stuck-together). Tests 4 and 5 write the exact same values as in test 3, but 8 bit write and 16 bit read is performed in test 4 while the opposite is performed in test 5. These tests make sure that the FIFOs can be accessed properly and also test the hardware interface such as the address lines, data lines and bus operation signals.

Interrupt Driven I/O Test
By performing the Interrupt Driven I/O we are testing to make sure that the TNT4882 can assert its interrupt line and that it gets acknowledged properly. Before we do any I/O we do a sanity check to make sure that the interrupt handler has been loaded properly. The program reads the contents of memory location $06C (IRQN3) and compares it with the address of the interrupt handler. If a mismatch occurs, the interrupt handler is not getting loaded properly, or the vector table is being altered which results in the loss of the handler address. Once the handler has been loaded properly, NFF bit of IMR3 is enabled. If FIFOs have room for a byte, an interrupt will occur. After writing to the FIFOs we enable the NEF bit of IMR3. An interrupt will occur if FIFOs contain bytes that need to be transferred to memory.

If the interrupts do not get acknowledged, chances are that the interrupt line is not connected properly. If an unexpected interrupt occurs, then your system may have deleted the address of the new handler from the exception vector table.

DMA I/O Test
DMA I/O tests the functionality of the DMA Channel and its associated interface logic. For example, when a DMA read is performed, data is transferred from memory (read from memory) to the TNT4882. If data transfers do not take place, chances are that WRN signal is not asserting during the DMA read cycle. Similarly, during a DMA write cycle, RDN should be asserted because data is transferred from FIFOs to memory.

In the DMA I/O test routine, the channel is initialized by clearing the status register and loading the byte transfer value in the byte counter register. The channel is then started, and DMA takes place when the DREQN1 pin of MC68340 goes low. DMA read takes place first where values are written to the FIFOs. DMA write takes place later where values are read back from the FIFOs.

MC340BUG Library

A Library is also included with the software package. The MC340BUG library provides basic I/O functions that use the M340BUG debug system calls. System calls use Trap #15 for I/O functions. Therefore Trap #15 is not available for user programs. The library was created using Microtec’s Librarian. This library package is only useful if you are developing programs using Microtec Research Software Development Tools.

Description of Library Functions

ERASLN()

Purpose	Erase the line at the present cursor position
Parameters	NONE
Return Type	void
Example	ERASLN();

NEWLN()

Purpose	Skip a line
Parameters	NONE
Return Type	void
Example	NEWLN();

getchar()

Purpose	Read a character from the input port
Parameters	NONE
Return Type	char
Example	c = getchar();

putchar()

Purpose	Write a character to the output port
Parameters	character to be written
Return Type	void
Example	putchar('a'); putchar(chr) where chr = 'z';

puts()

Purpose	Output a line to the output port
Parameters	string to be written
Return Type	void
Example	puts("hello"); puts(str) where str = "how are you?";

PrintHex()

Purpose	Output a number in hexadecimal form
Parameters	unsigned short int (0 - 65535)
Return Type	void
Example	PrintHex(321); PrintHex(num) where num = 3245;

RET340BUG()

Purpose	Restore control to 340Bug from the target program
Parameters	NONE
Return Type	void
Example	RET340BUG();

References

1. MC68340 Integrated Processor with DMA User’s Manual, Motorola Inc., 1992.
2. TNT4882 Programmer Reference Manual, National Instruments, 1994.
3. ESP-488TL Software Reference Manual for TNT4882, National Instruments, 1994.
4. M68340BUG Debug Monitor and Assembler User’s Manual, Motorola Inc., 1991.
5. M68340EVS Evaluation System User’s Manual, Motorola Inc., 1991.

   Appendix
   

See the Related Link to the <b>Appendix for "Using the TNT4882 in an MC68340 System"</b> (below) for these source files.

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