Settling Time Measurements of a PLL Chip

• NI LabVIEW
• PXI-5660 RF Signal Analyzer
• Spectral Measurements Toolkit
• Modulation Toolkit

PLL (phase-locked loop) and other timing chips are crucial components in almost every electronics design. They help provide important timing and clocking functions to the rest of the design. To ensure your PLL chip is functioning as advertised, settling time measurements are commonly used. Settling time is the time interval required for the PLL chip to move from one frequency to another and settle on the new frequency. The definition of "settled" usually requires that chip output be stable and within a range specified by the user. Because settling time measurements involve three parameters - frequency, time and amplitude - they are difficult to perform. However, the unique architecture of the PXI-5660 RF Signal Analyzer and powerful software toolkits combined with LabVIEW make these useful measurements possible.

The RF Signal Analyzer downconverts and digitizes the signal from the PLL chip. In software, the Modulation Toolkit converts the digitized IF data to complex I-Q data and performs FM demodulation on the incoming signal. This process allows the user to see a frequency vs. time signal plot which clearly shows chip output during frequency transition and settling. The user sets their own thresholds to define what "settled" means.

When the PLL transition bandwidth is 20 MHz or less, the RF Signal Analyzer can capture the entire band in real-time and show the transition from frequency f1 to frequency f2. When the PLL transition bandwidth exceeds 20 MHz, the digitizer portion of the RF Signal Analyzer can be triggered to begin acquisition concurrent with the beginning of the PLL transition. Next the RF Signal Analyzer tunes to frequency f2 and demodulates the incoming signal. When the demodulated FM data shows a stable level at frequency f2, the settling time is calculated on the basis of the digitizer acquisition start time and the time the stable level was reached at frequency f2. When plotting this transition, the user sees a large amount of "noise" before the signal settles. A screenshot of such a scenario is shown below.

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