Writing Functional Self-Tests for the TNT4882 GPIB Interface Chip

This document describes software that you can use to functionally test the TNT4882 GPIB interface chip. You can use this code as a part of the production test of a device or as part of the self test of the device. You can add or remove other tests as needed for a particular application.

The code (which is really pseudocode) is independent of the processor used in a device.

Removing the GPIB Cable During Tests?

In these tests, the TNT4882 chip verifies that it can assert certain GPIB signals. In a production test, this can be useful for detecting shorts or opens on the GPIB signal lines.

Note that if the TNT4882 chip is connected to a GPIB system, other devices may be driving the GPIB signals. The tests may fail unless the user removes all GPIB cables from the device running the self test. To avoid this problem, we recommend running self-tests with the WRAP bit set. The WRAP bit is bit 2 of the Miscellaneous Register (MISC).

When WRAP=1, the GPIB transceivers are tristated, but the GPIB signals are fed back into the TNT4882. So, the tests run successfully even with GPIB cables attached to the device.

Code Overview

The code is divided into three routines:

• TNT4882 Chip Reset routine – reset the TNT4882 chip
• I/O register test – verifies that the CPU can read and write registers of the TNT4882
• Interrupt tests – verifies that the TNT4882 can interrupt the CPU

Normally the reset routine is called both before and after the other tests run. So, a normal code flow would be:

• TNT4882 Reset
• Set or clear the WRAP bit (as needed)
• I/O register test
• Interrupt test
• TNT4882 Reset
• Clear the WRAP bit

Mnemonics Used in Code Listing
The code listings use the following mnemonics:

TNT4882 Chip Reset Routine

The following routine completely resets the TNT4882 chip. This test makes no assumptions about the initial state of the TNT4882 chip.

{WT,    tauxcr,   0x80},  /* chip reset if in 9914 mode */
{WT,     auxmr,   0x80},  /* swrst if swapped */
{WT,     tauxcr,  0x99},  /* switch to 7210 mode */
{WT,     auxmr,   0x99},  /* switch to 7210 mode if swapped */
{WT,     auxmr,   0x02},  /* execute chip reset */
{WT,     keyreg,  0x00},  /* important! clear the swap bit */
{WT,     eosr,    0x00},  /* clear EOS register */
{WT,     cdor,    0x00},  /* clear data lines */
{WT,     imr1,    0x00},  /* disable all interrupts */
{WT,     imr2,    0x00},
{WT,     imr0,    0x80},
{WT,     adr,     0x80},
{WT,     adr,     0x00},
{WT,     admr,    0x00},  /* clear addressing modes */
{WT,     auxmr,   0x00},  /* release from idle state with pon */
{WT,     auxmr,   0x60},  /* reset ppr */
{WT,     bcr,     0x00},  /* reset bcr */
{WT,     misc,    0x04},  /* set wrap plug bit */
{WT,     cmdr,    0xB2},  /* issue soft reset */
{WT,     hssel,   0x00},  /* select two-chip mode */
/* end */

I/O Register Test

The I/O register tests verify that the CPU can read and write registers of the TNT4882.

Read Initial Values
{RD,     isr1,    0x00},  /* Verify mask registers are clear */
{RD,     isr2,    0x00},
{RD,     adsr,    0x40},  /* Verify ATN is not asserted */
{RD,     adr0,    0x00},  /* Verify Primary address not set */
{RD,     adr1,    0x00},  /* Verify Secondary address not set */
{RD,     sts1,    0x8B},  /* Verify DONE, STOP, HALT, and GSYNC set */
{RD,     isr3,    0x19},  /* Verify STOP, Not Full FIFO, & DONE set */
{RD,     sts2,    0x9A},  /* Verify FIFO A/B is empty */
{RD,     sasr,    0x00},  /* Verify clear */
{RD,     isr0,    0x01},  /* Verify SYNC bit is set */

BSR & DCR
{WT,     bcr,     0x55},  /* Set DAV, NRFD, SRQ, and REN */
{WT,     dcr,     0xAA},  /* Write pattern to GPIB data lines */
{RD,     bsr,     0x55},  /* Verify DAV, NRFD, SRQ, and REN are set */
{RD,     dsr,     0xAA},  /* Verify data pattern written previously */
{WT,     bcr,     0xAA},  /* Set ATN, NDAC, EOI, & IFC */
{WT,     dcr,     0x55},  /* Write pattern to GPIB data lines */
{RD,     bsr,     0xAA},  /* Verify ATN, NDAC, EOI, & IFC are set */
{RD,     dsr,     0x55},  /* Verify data pattern written previously */
{WT,     bcr,     0x00},  /* Clear control lines */
{WT,     dcr,     0x00},  /* Clear data lines */
{RD,     bsr,     0x00},  /* Verify control lines are clear */
{RD,     dsr,     0x00},  /* Verify data lines are clear */

ADR0,1
{WT,     adr,     0x55},  /* Set Primary talk address */
{WT,     adr,     0xAA},  /* Set Secondary listen address */
{RD,     adr0,    0x55},  /* Read Primary address */
{RD,     adr1,    0x2A},  /* Read Secondary address */
{WT,     adr,     0x2A},  /* Set Primay listen address */
{WT,     adr,     0xD5},  /* Set Secondary talk address */
{RD,     adr0,    0x2A},  /* Read Primary address */
{RD,     adr1,    0x55},  /* Read Secondary address */

CDOR/DIR
{WT,     admr,    0xF0},  /* program AT-GPIB as talker only
                           * and listener only     */
{RD,     isr1,    0x02},  /* check DO bit set */
{RD,     adsr,    0x46},  /* check AT-GPIB is both talker
                           * active and listener active  */
{WT,     cdor,    0xAA},  /* write out data byte */
{DELAY,  0,          1},  /* One ISA I/O Cycle (500-ns) */
{RD,     isr1,    0x03},  /* check DO and DI bits set */
{RD,     dir,     0xAA},  /* verify data received */
{WT,     cdor,    0x55},  /* write out data byte */
{DELAY,  0,          1},  /* One ISA I/O Cycle (500-ns) */
{RD,     dir,     0x55},  /* verify data received */

SPMR/SPSR
{WT,     spsr,    0x00},  /* Write pattern to SPSR register */
{RD,     spmr,    0x00},  /* Read back previously written pattern */
{WT,     spsr,    0xBF},  /* Write pattern to SPSR register */
{RD,     spmr,    0xBF},  /* Read back previously written pattern */

COUNT 0:1
{WT,     cnt0,    0x55},  /* Verify every other bit can be set */
{WT,     cnt1,    0xAA},
{RD,     cnt0,    0x55},  /* Read back previously written pattern */
{RD,     cnt1,    0xAA},
{WT,     cnt0,    0xAA},  /* Verify every other bit can be set */
{WT,     cnt1,    0x55},
{RD,     cnt0,    0xAA},  /* Read back previously written pattern */
{RD,     cnt1,    0x55},

FIFO A/B
{WT,     cfg,     0x01},  /* set 16 bit mode */
{WTW,    fifob,   0x55aa},
{WTW,    fifob,   0xaa55},
{RDW,    fifob,   0x55aa},
{RDW,    fifob,   0xaa55},
{WT,     fifob,   0x55},  /* add element to B */
{RD,     isr3,    0x1D},  /* NFF, NEF set */
{RD,     sts2,    0xDB},  /* BFFN, BEFN set */
{WT,     fifoa,   0x55},  /* add element to A */
{RD,     isr3,    0x1D},  /* NFF, NEF set */
{RD,     sts2,    0xDF},  /* AFFN, AEFN set */
{RD,     fifob,   0x55},  /* remove element from B */
{RD,     isr3,    0x1D},  /* NFF, NEF set */
{RD,     sts2,    0xDE},  /* BEFN clear */
{RD,     fifoa,   0x55},  /* remove element from A */
{RD,     isr3,    0x19},  /* NEF clear*/
{RD,     sts2,    0xDA},  /* AEFN clear */
{WT,     fifob,   0xAA},  /* add element to B */
{WT,     fifoa,   0xAA},  /* add element to A */
{RD,     fifob,   0xAA},  /* remove element from B */
{RD,     fifoa,   0xAA},  /* remove element from A */

IMR3
{WT,     cmdr,    0x04},  /* send go command */
{RD,     isr3,    0x08},  /* Verify only NFF set */
{WT,     imr3,    0x00},  /* Verify all bits can be cleared */
{RD,     imr3,    0x00},  /* and set. Bit 7 cannot be written to. */
{WT,     imr3,    0x77},
{RD,     imr3,    0x77},
{WT,     cmdr,    0x08},  /* send stop command */
{WT,     imr3,    0x00},  /* Clear all interrupt conditions */
{WT,     fifoa,   0x1},   /* add element to A */
{WT,     fifoa,   0x2},   /* add element to A */
{WT,     fifoa,   0x4},   /* add element to A */
{WT,     fifoa,   0x8},   /* add element to A */
{WT,     fifoa,   0x10},  /* add element to A */
{WT,     fifoa,   0x20},  /* add element to A */
{WT,     fifoa,   0x40},  /* add element to A */
{WT,     fifoa,   0x80},  /* add element to A */
{WT,     fifoa,   0xfe},  /* add element to A */
{WT,     fifoa,   0xfd},  /* add element to A */
{WT,     fifoa,   0xfb},  /* add element to A */
{WT,     fifoa,   0xf7},  /* add element to A */
{WT,     fifoa,   0xef},  /* add element to A */
{WT,     fifoa,   0xfd},  /* add element to A */
{WT,     fifoa,   0xfb},  /* add element to A */
{WT,     fifoa,   0x7f},  /* add element to A */
{RD,     isr3,    0x15},  /* STOP, NEF, & DONE */
{WT,     imr3,    0x08},
{RD,     imr3,    0x08},
{WT,     imr3,    0x00},  /* Clear all interrupt conditions */
{WT,     cmdr,    0x10},  /* Reset FIFOs */

STS1
{RD,     sts1,    0x8b},  /* check IN bit cleared */
{WT,     cfg,     0x20},  /* set data Transfer to IN */
{RD,     sts1,    0xab},  /* Verify IN bit set */
{WT,     cfg,     0x00},  /* set data Transfer to OUT */
{RD,     sts1,    0x8b},  /* check IN bit cleared */

TIMER
{WT,     timer,   0x55},  /* Write bit pattern to timer */
{WT,     cmdr,    0x04},  /* Load pattern into counter
                             by asserting DRQ */
{WT,     cmdr,    0x08},  /* Clear DRQ */
{RD,     timer,   0x55},  /* Read counter part of timer */
{WT,     timer,   0xAA},  /* Write bit pattern to timer */
{WT,     cmdr,    0x04},  /* Load pattern into counter by
                             asserting by asserting DRQ */
{WT,     cmdr,    0x08},  /* Clear DRQ */
{RD,     timer,   0xAA},  /* Read counter part of timer */

COUNT 2,3
{WT,     cnt2,    0x55},  /* Verify every other bit can be set */
{WT,     cnt3,    0xAA},
{RD,     cnt2,    0x55},  /* Read back previously written pattern */
{RD,     cnt3,    0xAA},
{WT,     cnt2,    0x55},  /* Verify every other bit can be set */
{WT,     cnt3,    0xAA},
{RD,     cnt2,    0x55},  /* Read back previously written pattern */
{RD,     cnt3,    0xAA},

SASR
{WT,     auxmr,   0x51},  /* Immediate Holdoff */
{RD,     sasr,    0x10},  /* Acceptor Not Ready Holdoff Immediately *
{RD,     isr3,    0x19},  /* check NEF clear */
{WT,     imr3,    0x04},  /* allow NEF interrupt */
{WTW,    fifob,   0x00aa},/* set NEF */
{CKINT,  0,       bTrue}, /* check interrupt received */
{RD,     isr3,    0x1d},  /* check NEF set */

Interrupt Test

The interrupt test verifies that the TNT4882 can interrupt the CPU. It also check for spurious interrupts.

/* before running the following code,
 * you must enable the CPU to detect
 * hardware interrupts from the TNT4882
 */
{RD,     isr3,    0x19},   /* check NEF clear */
{WT,     imr3,    0x04},   /* allow NEF interrupt */
{WTW,    fifob,   0x00aa}, /* set NEF */
{CKINT,  0,       bTrue},  /* check interrupt received */
{RD,     isr3,    0x1d},   /* check NEF set */

DMA Testing Considerations

The code needed to test DMA accesses to the TNT4882 depends heavily on the nature of the system that uses the TNT4882. The following code segments describe one way to approach testing DMA accesses. In many places below, comments describe the type of actions the software should make.

DMA from the TNT4882 to System Memory
/* Initialize the system DMA controller */
{WT,     cmdr,    0x10},  /* reset fifo */
{WT,     cnt0,    0x00},  /* set count to 512 */
{WT,     cnt1,    0xfe},
{WT,     cfg,     0x17},  /* 16 bit write, A first, timeout
                           * enabled for Demand mode disabled
                           * for single cycle mode. */
{WT,     timer,   0xB0},  /* Timeout value = 10 us. */
{WT,     imr1,    0x04},  /* enable ERR */
{WT,     imr2,    0x20},  /* enable DMAO */
{WT,     admr,    0xf0},  /* set for listener and talker */
{WT,     cmdr,    0x04},  /* send GO */
/* Allocate 512 byte DMA buffer. */
/* Initialize DMA Buffer to variable data pattern */
/* Program DMA Controller for 512 Byte
 * transfer Demand mode, DMA Read. */
/* Start DMA */
/*
* Repeat the following 2 steps 512 times
*/
      /* Step 1: Wait for DI bit set in ISR1
       * If DI bit is not set within X amount of time
       * consider this a failure */
      {RD,     dir,        VAR}, /* Step 2: Read variable data
                                  * pattern from DIR */
{RD,     sts1,       0x8b},   /* check for DONE */
/* clean up after DMA operation
  */

DMA from System Memory to TNT4882
NOTE: Prepare board for DMA
{WT,     cmdr,       0x10},   /* reset fifo */
{WT,     cnt0,       0x00},   /* set count to 512 */
{WT,     cnt1,       0xfe},
{WT,     cfg,        0x31},   /* 16 bit read,A first */
{WT,     imr1,       0x10},   /* enable END */
{WT,     imr2,       0x10},   /* enable DMAI */
{WT,     admr,       0xf0},   /* set for listener and talker */
{WT,     cmdr,       0x04},   /* send GO */
/* Allocate and Initialize 512 byte DMA buffer. */
/* Program DMA Controller for 512 Byte
 * transfer Demand mode, DMA Write.
  */
/* Start DMA */
/*
 * Repeat the following 2 steps 512 times
  */
      /* Step 1: Wait for DO bit set in ISR1
       * If DO bit is not set within X amount of time
       * consider this a failure
       */
{WT, cdor, VAR},    /* Step 2: Vary pattern written to CDOR */
{DELAY},     /* Delay approx. 1 ms to allow for DMA transfer to finish */
{RD,     sts1,       0xab},   /* check DONE set */
/* clean up after DMA operation */
/* Verify that DMA buffer contains variable
* data pattern written
*/

Reader Comments | Submit a comment »