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In the following document, learn how to use signal generators, digital-to-analog converters, filters, onboard memory, and advanced clocking engines to generate a variety of analog signals.
Table of Contents
Introduction
This tutorial is part of the National Instruments Signal Generator Fundamentals series. Each tutorial in this series will teach basic concepts about the architecture, features, or applications of signal generators.
National Instruments signal generators use the synchronization and memory core (SMC) architecture to provide a common interface between onboard memory, external hardware, and the digital-to-analog converter (DAC) of the device. In this white paper we will differentiate between two types of signal generators - arbitrary function generators and arbitrary waveform generators. In addition, we will discuss various aspects of signal generators including the memory architecture, DAC considerations, digital gain, filtering and interpolation, the signal generation engine, and various events. A block diagram of a typical signal generator is shown below.
Figure 1. Signal Generator Block Diagram
In the following sections, we will discuss the role of each component in the generation of a signal. In addition, we will provide the technical details necessary for a user to generate the best possible signal with a signal generator. Note that signal generators vary according to type and function. For example, arbitrary function generators typically use less than 1 MB of onboard memory. Arbitrary waveform generators, on the other hand, use up to 512 MB of onboard memory and advanced sequencing capabilities. In addition, some arbitrary waveform generators implement onboard signal processing (OSP) for generation of baseband IQ and IF signals. Because OSP is not discussed in this whitepaper, refer to Introduction to OSP for more information.
Types of Signal Generators
Most signal generators contain common components such as a DAC, onboard memory, and either analog or digital filtering circuitry. However, signal generators can be divided into two types, depending on their memory options and clocking characteristics. These two categories are function generators and arbitrary waveform generators (AWGs). Below, we will distinguish each and describe the fundamental architecture.
Function Generators
Function generators are designed to generate periodic waveforms at precise frequencies. In fact, they typically use a clocking mechanism known as direct digital synthesis (DDS) to generate precise frequencies of with better than 1 µHz of precision. In addition, DDS provides function generators with the ability to change frequencies on the fly in a phase-continuous manner. Moreover, because function generators output repetitive waveforms, they require only limited memory to store a single period of the waveform. National Instruments arbitrary function generators are able to generate many periodic waveforms either from a standard library including: sine, square, ramp, and triangle waveforms; or from a user-defined waveform of 16 ksamples. Some common applications of function generators include filter characterization, stimulus-response testing, and clock sourcing.
Arbitrary Waveform Generators
AWGs, on the other hand, are designed to generate large and often complex waveforms. As a result, AWGs use deep onboard memory and sophisticated clocking mechanisms. In fact, the SMC architecture handles memory up to 512 MB. In addition, they are capable of advanced linking, looping, and scripting of waveforms for even more complex sequences. In addition, the SMC offers many advanced marker and trigger features for synchronization with other instruments. These features are discussed in more depth in a later section of this whitepaper.
Deep Onboard Memory
Modern signal generators (especially AWGs) implement deep onboard memory to store large waveforms. PCI or PXI-based instruments are able to use this memory effectively because of the high throughput possible on the PCI bus.
Signal generators use onboard memory to store both waveforms and sequence instructions. The instructions for a complicated sequence can occupy a significant block in memory. In fact, with the architecture of NI signal generators, you can load multiple waveforms and multiple sequence instructions into memory of the same instrument. The following diagram illustrates memory allocation on a typical NI signal generator.
Figure 2. Signal Generator Memory Allocation
Note that NI signal generators, with up to 512 MB onboard memory, have significant play times. Moreover, with the NI-FGEN driver, these waveforms can be written and overwritten in memory while the signal generator is generating a waveform. Thus, with the high throughput available on the PCI bus, you can continuously overwrite waveform segments for streaming generation.
Digital-to-Analog Converter (DAC)
Modern signal generators use an advanced DAC to convert digital waveforms in memory into analog signals. All DACs used by National Instruments operate with a sample-and-hold feature where the DAC will hold a discrete voltage level for a given period of time. For a more thorough discussion of choosing the right sampling rate, please see Introduction to High-Frequency Analog Signals. In addition, many digital-to-analog converters are able to implement interpolation to increase the effective sampling rate. For more information, please see Filtering and Interpolation to Improve Spectral Purity.
Digital Gain and Attenuation
Because signal generators are designed to generate signals over a wide range of voltage levels, both analog gain amplifiers and digital gain processing is used for to maximize both the amplitude accuracy and the flexibility of the signal generator.
NI Signal generators typically offer three distinct gain paths to amplify the analog output of the DAC to different analog voltage ranges. Example output for each of these paths is illustrated in the figure below:
Figure 3. Signal Generator Gain Amplifiers
In addition, signal generators also implement digital gain to amplify or attenuate signals to use the full range of the DAC. With this feature, the samples are scaled by the gain factor digitally before being generated as an analog sample. As a result, the amplitude of a given signal can be adjusted on the fly without needing to reload a different waveform into memory. Waveforms can be amplified up to the maximum range for a given signal path.
Interpolation and Filtering
As mentioned previously, DACs are only able to approximate truly ideal signals. In fact, because these stepped output of a DAC results in high-frequency images, modern signal generators implement both analog and digital filters to provide the best approximation of an ideal analog signal. As an example, the time domain of unfiltered signal is shown below.
Figure 4. DAC Sample-and-Hold Output
As a result of the sample-and-hold output, high-frequency images are produced. These images occur at each multiple of the sampling rate, plus or minus the fundamental tone. Thus, when generating a 20 MHz sinusoid sampled at 100 MHz, you will see images at 80, 120, 180, 220, ... MHz. Below, we show the frequency domain of the 20 MHz sine wave.
Figure 5. Spectral Images of a 20 MHz Sine Wave
As the graph illustrates, high-frequency spectral images can distort the frequency domain of the signal being generated.
National instruments signal generators use an analog and/or digital filter to remove high-frequency images. First, a digital finite-impulse response (FIR) filter interpolates the signal to increase the effective sampling rate. For example, suppose a 20 MHz sine wave is sampled at 100 MS/s and interpolated by 4X to an effective sampling rate of 400 MS/s. By increasing the effective sampling rate, the nearest spectral images of are moved to center around the new effective sampling rate as shown below:
Figure 6. Spectral Images of a 20 MHz Sine Wave with 4X Interpolation
As the figure above illustrates, digital filtering (interpolation) cannot eliminate spectral images entirely. Instead, it merely shifts them to a higher frequency. However, many signal generators also use an analog filter as well. The analog filter is able to attenuate these spectral images below the noise floor. This is illustrated in the image below, which shows the same frequency domain once a lowpass analog filter has been applied.
Figure 7. 20 MHz Sine Wave with Interpolation and Analog Filter
As the figure above illustrates, the spectral images have been dropped to below the noise floor of the device. In this specific example the analog lowpass filter attenuates high-frequency images by as much as 60 dB. As a result, the signal generator is able to produce an analog signal that is a more accurate approximation of an idea analog signal. Thus, we can observe the time domain of the interpolated and filtered signal in the figure below:
Figure 8. Time Domain of 20 MHz Sine Wave
As the image above illustrates, the individual steps once evident in the time domain are no longer visible. Instead, the output appears like a pure sinusoid. Thus, interpolation, and analog filtering both contribute to the ability of a signal generator to accurately approximate an analog signal. For a more thorough tutorial on how filtering and interpolation affects spectral purity, see the following document: Filtering and Interpolation to Improve Spectral Purity
Clocking
Just as the resolution of a DAC has a profound effect on the amplitude accuracy of the signal generated, the clock supplied to the DAC effects the frequency accuracy of the signal generated. As a result, the affects of an accurate clocking mechanism are measurable in the frequency domain of a signal. Modern signal generators offer a variety of ways to clock the output of the DAC at precise frequencies, with minimal clock jitter. In the following sections, we will describe each clocking mechanism and discuss the advantages that each provides.
Divide-by-N
Divide-down (or divide-by-N) clocking divides a signal generator timebase to derive a unique frequency. This component uses a voltage-controlled crystal oscillator (VCXO) to generate a fundamental high-frequency timebase for the signal generator. From this timebase, the divide-by-N circuitry is able to derive frequencies that are integer divisions of the signal generator timebase. For the example a timebase of 200 MHz can be divided into frequencies such as 200, 100, 66.6, and 50 MS/s.
The divide-by-N clocking mechanism is preferred when possible because it offers the lowest jitter of the sample clock. However, it is also the least flexible clocking mechanism because valid sample rates must be an exact divisor of the timebase.
High-Resolution Clocking
A second clocking option for signal generators is high-resolution clocking, which enables the most precise frequency resolution. With this mechanism, it is possible to derive a sample clock up to the maximum rate, even if it is not a divisor of the fundamental timebase. National Instruments signal generators use this clocking mechanism to derive clocks to better than 1 µHz of precision. This clocking mode is useful for applications that require a precise clock frequency, which is not possible using the divide-down clocking scheme. However, high-resolution clocking has the disadvantage in that results in more clock jitter than the divide-by-N mechanism.
Direct Digital Synthesis (DDS)
National Instruments function generators use a clocking mechanism known as direct digital synthesis. DDS works by first storing a large repetitive waveform into a finite memory space. For National Instruments products, any single cycle of a waveform (sine, triangle, square, and arbitrary) can be represented by exactly 16,384 points and stored into memory. Once the waveform is stored into memory, it can be generated at very precise frequencies.
It is important to note that generation of a waveform using DDS is fundamentally different than arbitrary waveform generation. With arbitrary waveform generation, each sample of the waveform is stored into memory and generated in a sequential manner. Signals generated with DDS operate slightly differently. With this mechanism, a single period of a waveform is stored into memory. However, when generating the signal, the DAC does not generate every point in the waveform. Instead, when generating a precise frequency, the DAC will skip samples in generation to produce the desired sampling rate. We illustrated this in the graph below:
Figure 9. Generating a 21 MHz Signal with Direct Digital Synthesis
The implementation of DDS requires a look-up table to determine the phase of the signal to generate at any point in time. The following figure shows the building blocks for direct digital synthesis-based waveform generation.
Figure 10. Functional Blocks of Direct Digital Synthesis
As the figure above illustrates, a phase accumulator compares the sample clock and desired frequency to increment a phase register. The fundamental principle is that DDS enables the generation of periodic signals at precise frequencies by selecting the appropriate sample according to the desired instantaneous phase of the signal. By representing our waveform with 214 (16,384) points, we are able to represent exactly 16,384 phase increments with our lookup table. Because of DDS, function generators are able to generate signals at precise frequencies. In fact, with 48-bit DDS, NI 5406 devices offers frequency precision of better than 1 µHz.
For more information on how DDS enables precise frequency generation, please see Using Direct Digital Synthesis (DDS) for Precise Frequency Generation.
Reference Clocking
While the sample clock is used by the signal generator to determine the timing of new sample generation, a reference clock is important for synchronizing multiple instruments. When using a reference clock, a signal generator is able to phase-lock its sample clock with an external clock through a phase-lock loop (PLL). A PLL is a feedback circuit that is able to align the phase of a sample clock with a reference clock (see Figure 11). As a result, by sharing the same reference clock between multiple devices, we are able to synchronize the sample clocks and align the signals generated. The following figure shows a block diagram of a basic PLL.
Figure 11. Basic Phase Locked Loop Circuit
As the block diagram illustrates, a PLL is a feedback control system that controls the phase of a voltage-controlled crystal oscillator (VCXO). The frequency reference signal is applied to a phase detector. The phase detector outputs a voltage that is proportional to the phase difference between the two input signals. Finally, the loop filter then adjusts the phase of the oscillator clock to match the phase of the reference signal. As a result, the reference frequency and the sample clock can perfectly match in phase.
Linking and Looping (Waveform Generation Engine)
NI signal generators use advanced SMC features for linking and looping of waveform segments. Linking and looping can be divided into two generation modes, sequence mode and script mode. With sequence mode, you can configure a signal generator to output a predetermined series of waveforms with sequence instructions stored in the onboard memory. Script mode, on the other hand, is even more powerful because with it you can create a dynamic waveform sequence in which the signal generator output is dependent on the state of a hardware or software trigger. In addition, script mode uses conditional statements such as "If/else" to implement branching waveform sequences. With both linking and looping modes, the signal generator can be configured to output one or multiple trigger signals with features such as the marker or marker event. For more information on how to use the SMC architecture for advanced timing and synchronization, please see Advanced Sequencing and Triggering with Signal Generators.
Sequence Mode
In sequence mode, you can generate a series of waveforms through a preconfigured sequence. In addition, you can implement various triggering modes to advance to the next waveform in the sequence. Common trigger modes include single trigger, continuous trigger, stepped trigger, and burst trigger. Each of these modes provides different output options when each waveform is generated. As an example, stepped trigger mode is described below.
In stepped trigger mode, a trigger is used to step through each waveform in a sequence list. When the generation session is started, the first waveform will loop as many times as has been configured for that particular step. After the waveform has been looped for the appropriate number of iterations, the last sample of the waveform repeats continuously until the next trigger is received. When the next trigger is received, the second waveform will be generated for the configured number of iterations. This process repeats until the last of the configured waveforms has been generated. At this point, a trigger condition is required to start the generation sequence again. This is illustrated in the figure below:
Figure 12. Sequencing with Stepped Trigger Mode
As Figure 12 illustrates, the signal generator begins generating the first waveform at time t0 when the first trigger is received. In addition, it will continue to loop through generation of "waveform0" until it reaches the number of configured loops (twice in this case). As we can observe in the figure above, the signal generator will continue to drive the last sample of "Waveform0" until time t1, when the next trigger is received.
Script Mode
While sequence mode enables a signal generator to output a series of waveforms upon receiving triggers, it does have its limitations. Fundamentally, sequence mode requires each step to be configured before signal generation begins. In order to configure a dynamic script, where the output is conditional, a more advanced form of sequencing called scripting must be used.
Scripting enables a signal generator to dynamically output a sequence of waveforms based on hardware or software events in the system. In addition, it is the most advanced waveform control feature because of its flexibility. With scripting, not only can you link and loop between multiple waveforms, but you can also generate a waveform conditional on an event that occurs in the device under test with the configuration of a script trigger. With a script trigger, the scripting engine dynamically chooses the waveform to generate, depending on the state of a particular trigger line.
As an example, consider a script that uses the "Repeat until" command. With this script, "waveform1" is configured to repeat until the script trigger becomes true. The specific script is shown below.
Figure 13. Example Script Using the "Repeat until" Command
Notice that "scriptTrigger0" is being used as the variable that determines which waveform should be generated. In this specific script, the signal generator will begin by generating "waveform0" first. Once this waveform has been generated, it will loop through generating "waveform1" and will continue to repeat this waveform until "scripttrigger0" changes to True. Once this event occurs, the signal generator will generate "waveform2" before finishing the sequence. Thus the output signal resulting from this script is shown below:
Figure 14. Signal Generator Output with the "Repeat until" Script
As the figure above illustrates, we can see that the signal generator will continue to generate "waveform1" until "scripttrigger0" evaluates to TRUE. Thus, scripting enables you to generate dynamic waveforms by configuring a script trigger to determine the output of the signal generator. For information on how scripting enables generation of advanced signals, see Advanced Sequencing and Triggering with Signal Generators.
Trigger and Events
For synchronization with other instruments, the SMC architecture offers features such as the marker event and data marker event. Using these events, you can configure your signal generator to generate output triggers to control the behavior of other instruments. With marker events, you can configure up to one (sequence mode) or four (script mode) trigger lines to change state synchronous with a configured sample number. By contrast, with the data marker event, you can route up to four bits of the analog waveform to up to four trigger lines. With this type of output trigger, the state of the trigger is embedded into the actual waveform.
Marker Events
Marker events are specified by giving an offset (in number of samples) from the start of the waveform. In sequence mode, you configure one marker event for each step in the sequence. In script mode, you can configure up to four markers at different offsets of a particular waveform. As we can see in the diagram below, the trigger line associated with the marker becomes asserted on the same clock edge that generates the 20th sample. In addition, we can observe that in this particular case, the trigger line is to be asserted for 40 periods of the sample clock frequency.
Figure 15. Timing of Marker Event Output
Note that the behavior of the marker output can be configured in a number of ways with a property node. As the diagram above illustrates, the marker event has been configured as a pulse for eight periods of the sample clock.
Data Marker Event
With the data marker event, you can export up to four waveform data bits to a physical trigger line as a digital signal. For example, typical signal generators use a 16-bit DAC; 16-bit samples are sent to the DAC at every period of it sample clock. However, up to four bits of each sample can be routed to physical trigger lines as well. Thus, these four waveform bits can be configured as a digital waveform for synchronization with other hardware. Although you can choose any four bits, the four least significant bits are typically used so that the analog output is least affected. A timing diagram of a signal using data bit markers is shown below.
Figure 16. Bitwise Representation of a Waveform
As the diagram above illustrates, the four least significant bits of each 16-bit sample have been highlighted. Using the data marker event, each of these bits are directly routed to a trigger line as a digital signal. For more information on how to use the SMC for synchronization with other instruments, see Advanced Sequencing and Triggering with Signal Generators.
Conclusion
Modern signal generators utilize the synchronization and memory core (SMC) architecture to enable the generation of complex and accurate analog signals. As a result, signal generators are able to generate a large variety of signals and service a wide array of applications. For more information on various features that are implemented to achieve this, please see: Signal Generator Fundamentals. For more information on the applications that typically utilize signal generators, please see: Signal Generators Applications Main Page.
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