I2C Bus Overview

An overview of the I2C (Inter Integrated Circuit) bus, commonly used for communication between ICs on a circuit board. This tutorial covers the low-level basics of the bus, which includes data transfers, arbitration, and addressing. It also discusses the basic read/write and where to find the shipping examples.

I²C Bus

The I² C bus is a two-wire half-duplex serial interface. The two lines, Serial Data (SDA) and Serial Clock (SCL), are both bidirectional.

The I² C specification defines three speeds: standard, 100 kHz; fast, 400 kHz; and high speed, 3.4 MHz.

Each device connected to the I²C bus has a unique 7-bit I²C address to facilitate identification and communication by the master. Typically, the upper four bits are fixed and assigned to specific categories of devices (for example, 1010 is assigned to serial EEPROMs). The three lower bits are programmable through hardware address pins, allowing up to eight devices of the same type to be connected to a single I² C bus.

Each device on the bus (both master and slave) can be a receiver and/or transmitter. For example, an LCD is typically only a receiver, while an EEPROM is both a transmitter and receiver.

The I²C is a multi master bus, meaning that multiple masters can be connected to the bus at the same time. While a master is initiating a transfer on the bus, all other devices, including other masters, are acting like slaves. However, if another master is trying to control the bus at the same time, I² C defines an arbitration mechanism to determine which master gets control of the bus.

I²C Transfers

To initiate a transfer, the master issues a start condition by changing the SDA line level from high to low while keeping the SCL clock line high. When this occurs, the bus is considered busy, and all devices on the bus get ready to listen for incoming data.

Next, the master sends the 7-bit address and 1-bit for data transfer direction on the bus to configure for the appropriate data transfer. All slaves compare the address with their own address. If the address matches, the slave produces an ACK (acknowledge) signal.

If the master detects an ACK signal, it starts transmitting or receiving data. To transmit data to a device, the master places the first bit onto the SDA line and generates a clock pulse to transmit the bit across the bus to the slave. To receive data from a device, the master releases the SDA line, allowing the slave to take control of it. The master generates a clock pulse on the SCL line for each bit, reading the data while the SCL line is high. The device is not allowed to change the SDA line state while the SCL line is high.

After the data transmission, the master issues the stop condition by changing the SDA line from low to high while keeping the SCL clock line high. When this occurs, the bus is considered free again for another master to initiate a data transfer.

(A) Bus Not Busy: Both data and clock lines remain high.

(B) Start Data Transfer: A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.

(C) Stop Data Transfer: A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition.

(D) Data Valid: The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device.

Acknowledge Timing

A device that ACKs must pull down the SDA line during the ACK clock pulse in such a way that the SDA line is stable low during the high period of the ACK related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an ACK bit on the last byte that has been clocked out of the slave. In this case, the slave will leave the data line high to enable the master to generate the Stop condition. 

Example of the ACK Timing

I2C Clock Stretching

Because the master controls the clock, the I2C specification provides a mechanism to allow the slave to slow down the bus traffic when it is not ready. This mechanism is known as clock stretching. During any SCL low phase, a slave may additionally hold down SCL to prevent it from rising high again to slow down the SCL clock rate or pause I2C communication.

When the master attempts to make SCL high to complete the current clock pulse, it must verify that it has really gone high. If it is still low, it knows a slave is holding it low and must wait until it goes high before continuing.

I2C Extended (10-Bit) Addressing

Typical I2C devices use a 7-bit addressing scheme. I2C also defines a 10-bit addressing scheme that allows up to 1024 additional addresses to be connected to the I2C bus. This 10-bit addressing scheme does not affect the existing 7-bit addressing, allowing both 7-bit and 10-bit addressed devices to share the bus.

A device that supports 10-bit addressing receives the address across two bytes. The first byte consists of the Philips-designated 10-bit slave addressing mode code (11110), the 2 MSBs of the device address, and the Read/Write bit. The next data byte sent across the bus contains the eight LSBs of the address.

I²C Arbitration

When two masters are trying to control the bus simultaneously, or if a second master joins the bus in the middle of a transfer and wants to control the bus, the I² C bus has an arbitration scheme to guarantee no data corruption.

With I²C, a line (both SDA and SCL) is either driven low or allowed to be pulled high. When a master changes a line state to high, it must sample the line afterwards to make sure it really has been pulled high. If the master samples the SDA bus after setting it high, and the sample shows that the line is low, it knows another master is driving it low. The master assumes it has lost arbitration and waits until it detects a stop condition before making another attempt to start transmitting.

I²C Pin Description

A0, A1 and A2 Chip Address Inputs:

The A0, A1 and A2 inputs are used for multiple device operations. The logic levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using different Chip Select bit combinations.

These inputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’.

For applications in which these pins are controlled by a microcontroller or other programmable logic device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed.

Serial Data (SDA):

This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore, the SDA bus requires a pull up resistor to VCC. (typically 2.2 or 4.4 kOhm)

For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.

Serial Clock (SCL):

This input is used to synchronize the data transfer from and to the device.

Write-Protect (WP):

This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC write operations are inhibited but read operations are not affected.

Using the USB-8451 LabVIEW API with I² C

The National Instruments USB-8451 is an interface for connecting to and communicating with I²C, SMBus, and SPI devices. With plug-and-play USB connectivity, the NI USB-8451 is a portable solution to communicate with consumer electronics and integrated circuits. It also includes eight general-purpose digital I/O lines for a variety of applications, such as configuring the address of I²C devices or toggling LEDs.

The USB-8451 can be physically located more closely to I²C/SPI devices than PCI interfaces, reducing I²C bus length and minimizing noise problems. Additionally, the interface provides +5 V and GND to power circuits up to 230 mA with no external power supply.

Device Addressing

A control byte is the first byte received following the Start condition from the master device. The control byte consists of a 4-bit control code, typically set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1 and A0).

The Chip Select bits allow the use of up to eight devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address.

The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected and when set to a zero a write operation is selected.

Example of the control byte format

Basic LabVIEW API for Device Addressing

Use the property node to define the device address. If only one slave is connected to CS 0 the address is typically h50 (1010000- see control byte format above). The configuration output goes then to the high level Write, Read or Write/ Read VIs.

Property Node for 845x Basic API

Advanced LabVIEW API for Device Addressing

Use the Script Address + Write or + Read Functions after a Script Issue Start function to program the device address.

Write Operation

Byte Write

Following the Start condition from the master, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is logic low for write operations) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address byte (for single address byte) or bytes (for two address bytes) will follow after it has generated an ACK bit during the ninth clock cycle.

Therefore, the next byte transmitted by the master is the high byte of the word address and will be written into the Address Pointer. The next byte is the Low Address Byte. After receiving another ACK, the master device will transmit the data word to be written into the addressed memory location. The slave ACKs again and the master generates a Stop condition. This initiates the internal write cycle (from the buffer to the memory) and during this time, the Slave will not generate ACK signals.

Example of a Byte Write

Page Write

The write control byte, word address and the first data byte are transmitted to the slave receiver in the same way as in a Byte Write. But instead of generating a Stop condition, the master transmits up to 127 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. After receipt of each word, the seven lower Address Pointer bits are internally incremented by one. If the master should transmit more than 128 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the Byte Write operation, once the Stop condition is received, the internal write cycle will begin (from the page buffer to the memory).  Refer to Figure 8 for an example of a Page Write.

Example of a Page Write

Note: You need to look at the page size of your chip!

Page Write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1].

If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.

Basic LabVIEW API for Write Operations

The basic write operation takes the device descriptor, the configuration reference (including the device address) and uses a data byte array to write the data bytes to the address specified in the first two bytes.

The write functions acts like it is described above. To write to single byte addresses use a U8 integer instead of the U16 for the first data byte.

Example of 845x Basic API Write Operation

Advanced LabVIEW API for Write Operations

Use the Script write function twice to write the EEPROM Start address and the data bytes, followed by the Issue Stop function to have the same result as using the basic function.

Example of 845x Advanced API Write Functions

Read Operation

Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to ‘1’. There are three basic types of read operations: current address read, random read, and sequential read.

Current Address Read

The slave normally contains an address counter that maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous read access was to address ‘n’ (n is any legal address), the next Current Address Read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to ‘1’, the slave issues an ACK and transmits the 8-bit data word. The USB-8451 will not ACK the transfer but does generate a Stop condition and the Slave discontinues transmission. 

Example of Current Address Read Operation

Random Read

Random Read operations allow the USB-8451 to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the slave as part of a write operation (R/W bit set to ‘0’). After the word address is sent, the master generates a Start condition following the ACK. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues the control byte again but with the R/W bit set to a one.

The slave will then issue an ACK and transmit the 8-bit data word. The USB-8451 will not ACK the transfer but does generate a Stop condition which causes the Slave to discontinue transmission. After a Random Read command, the internal address counter will point to the address location following the one that was just read.

Example of Random Read

Sequential Read

Sequential Reads are initiated in the same way as a Random Read except that after the slave transmits the first data byte, the master issues an ACK as opposed to the Stop condition used in a Random Read. This ACK directs the slave to transmit the next sequentially addressed 8-bit word (Reference the Example of Random Read). Following the final byte transmitted to the master, the master will not generate an ACK, but will generate a Stop condition.

To provide Sequential Reads, a slave normally contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address FFFF to address 0000 if the master ACKs the byte received from the array address FFFF. 

Example of Sequential Read

Basic API for Read Operations

For the Basic API, we have two different VIs to reflect two different ways to read data. The easiest way is to read the current address as described in the Read Operations section. Therefore you need to use the Read VI and the Read process starts at memory address ‘0’ and the next time behind the last address you read. This is because you do not specify which start address to use and the slave uses his address counter that maintains the address of the last word accessed.

Example of 845x Basic API Read for Current Address

The second way to read data using I2C is using the Write/Read Function. For the Random and Sequentially Read this function performs a Write to specify the Start address to read from and a Read to read the data from this address. The Random Read reads only a single byte on a random position specified by the start address. The Sequentially Read reads as much data as specified with Number of Bytes to Read.

Example of 845x Basic API Read Write for Random and Sequentially Read Address

Advanced API for Read Operations

The 845x Advanced API allows you to script individual functions. For the Current Read, you have to write the address together with the read bit ‘1’, before you can read from the current address. For the Random and Sequentially Read you have to write the address and the write command bit ‘0’ before you can write the Start address. Then you have to write the address again together with the read bit ‘1’ to read any data. Both operations are separated by the Issue Start command.

Example of 845x Advanced API for Current Read

Example of 845x Advanced API for Random or Sequentially Read

Finding Examples

Where to find examples on a Windows XP system:

• LabVIEW
  
  Open LabVIEW » Help » Find Examples ... » Hardware Input and Output » I2C and SPI
• CVI
  
  C:\Program Files\National Instruments\CVIXX\samples\ni845x

• Microsoft Visual C/C++ 6.0
  
  C:\Program Files\National Instruments\NI-845x\MS Visual C\Examples

Note: To find the shipping examples on your computer, you will need to download the NI-845x Driver which can be found in the Related Links section.

 

SPI Bus

SPI Bus

The SPI bus is a four-wire, full-duplex serial interface. Three of the wires, SCK, MOSI, and MISO, are shared along with a fourth wire, known as the chip select, which is a direction connection between the master and a single slave.

Communication across SPI uses a system known as data exchange. Whenever a bit is written to an SPI device across the MOSI lines, the SPI device concurrently returns a bit on the MISO line. Because data is transferred in both directions, it is up to the receiving device to know whether the received by is meaningful or not. For example, to receive data from an EEPROM, the master must configure the EEPROM to send n bytes of data and then must send n bytes to be exchanged for valid data. These bytes can usually be any value, and writing them serves only to clock the data out of the receiving device.

For more information please reference the following Developer Zone Tutorial: Using the National Instruments USB-8451 I2C and SPI Interface to Evaluate a Texas Instruments Analog.

Related Links

• Product Page: NI USB-8451 I2C/SPI Interface
• Drivers and Updates: NI-845x 1.1.1 - Windows 2000/Vista x64/Vista x86/XP
• KnowledgeBase 3VMGBS5N: How Do I Access My 8451 From LabVIEW?
• KnowledgeBase 3VGF8CUX: Available Clock Rates on the NI USB-8451
• KnowledgeBase 3VTGEC2W: Using NI-845x i2c and SPI Refnums with TestStand
• Developer Zone Tutorial: Implementing I2C Communication Protocol in LabVIEW FPGA

 

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