Pulse Width Modulation Example DAQ Personality

This document is part of the Customize Your DAQ Device series. This document specifically describes the high channel count Pulse-Width Modulation (PWM) example personality. The PWM personality was designed to target high channel count needs for both PWM output and input. Currently, there is not a DAQ device capable of more than 4 PWM outputs. The current solution is to use multiple DAQ boards capable of PWM and synchronize their outputs. This personality alleviates that need by customizing a DAQ board to have sixteen PWM channels configurable for input or output. The attached host example code uses 12 PWM outputs and 4 PWM inputs.

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LabVIEW FPGA Personality

The LabVIEW FPGA code is the portion of this code embedded on the R Series  board.  This code defines the FPGA in the same way an ASIC defines a MultifunctionDAQ board.  This code was written with LabVIEW FPGA and compiled into a bitfile.  It is in its finalized form and does not require LabVIEW FPGA to be used.  However, to customize this code LabVIEW FPGA is required. 

This LabVIEW FPGA personality implements the Single Cycle Timed Loop (SCTL) architecture, with each SCTL dedicated to a specific DIO line.  Here is a look at the Block Diagram for the LabVIEW FPGA code:

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Figure 1: Block Diagram of the LabVIEW FPGA code

PWM

Each SCTL on the block diagram is dedicated to a particular DIO line and has the flexibility to perform PWM output or input.  This functionality is defined by a simple case structure and Boolean control.  If the Boolean is set to a false value, the DIO line will be used for PWM output.  If the Boolean is set to a true value, the DIO line will be used for PWM input.  These two cases are shown below for DIO line 0:

 
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 Figure 2: Single Cycle Timed Loop Dedicated to DIO Line 0 (Both cases)

PWM Input

For PWM input, a digital line is monitored at the rate of the FPGA clock (it is 40 MHz in this case).  The FPGA code counts the number of ticks, also known as clock pulses, that occur during both the low time and high time of the incoming signal.  Those values are stored on the FPGA in the Low Period and High Period numeric indicators.  These values can then be read by the Host VI which resides on the user’s computer.  This will be discussed in more detail in the upcoming sections. 

The PWM input logic is shown below: 

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Figure 3: PWM Input Logic (contained in a subVI)

PWM Output

For PWM output, the FPGA code is also run at the rate of the FPGA clock.  The user provides the FPGA with the number of ticks desired for a high time and low time.  The FPGA will output and sustain high or low for the duration of ticks desired.

The PWM output logic is shown below: 

 

Figure 4: PWM Output Logic (contained in a subVI) 

Digital IO

The LabVIEW FPGA architecture makes it simple to add additional loops in parallel without affecting other parts of the FPGA application.  For this reason, the LabVIEW FPGA code also takes advantage of the remaining DIO lines by configuring all of Connector 1 as static digital outputs and all of Connector 2 as static digital inputs.  This FPGA code is shown below:

Figure 5: Static DIO Logic

LabVIEW Host Personality

The LabVIEW Host code acts as the User Interface used to communicate with the FPGA.  The Host code interacts directly with the FPGA code by updating controls and reading from indicators on the Front Panel of the FPGA code.  This functionality is supported by the NI-RIO driver. 

This example personality consists of three main steps:

1.      Open a reference to the FPGA bitfile on the target R Series board.

2.      Use a Read/Write Node to update controls and indicators on the FPGA Front Panel.

3.      Close the reference to the FPGA bitfile.

Block Diagram

Here is a look at the example Host Block Diagram:

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Figure 6:  Block Diagram of the LabVIEW Host Code

These three main steps outlined above describe the overall setup of the Host VI.  This Host code is a little more complex because of conversions that must take place prior to writing to a control.  The following sections are going to explain these three main steps in more detail:

1.      Open Reference to Target FPGA

Figure 7: First Part of the Host Code

The first part of the code is the initialization stage.  In this part of the code, the resource name for the target R Series board is passed to the Open FPGA VI Reference.  This function opens a reference to the board that can be used by any subsequent functions or subVIs that communicate with the FPGA.  The reference is then passed to the Read/ Write Node and the digital lines are initalized to function as an output or input.  Finally, the Invoke Method node is used to start the FPGA code on the R Series board.    

2.      Read FPGA Indicators and Write to FPGA Controls

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Figure 8: Middle Part of the Host Code

The middle part of the code will consume the majority of the execution time for this Host VI.  This part of the code consists of a while loop with a Read/ Write node inside of it.  The Read/ Write node allows users to write to controls and read from indicators on the front panel of the FPGA code.  In the figure shown above, each input to the node is a control in the FPGA code. 

For example, “Output 0 – Low Time (Ticks)” is the name of a control in the FPGA code.  This particular control defines how many ticks DIO line 0 will output a low value.  That control paired with “Output 0 – High Time (Ticks)” defines a PWM output channel (the high time and low time correlate to a frequency and duty cycle).  Refer to figure 1 to see these controls being used on the FPGA. 

LabVIEW FPGA only supports integer math and integer data-types.  For this reason, the data type written to the FPGA code must be an integer (in this case it is a U32) and any division necessary must be done on the host.  The intermediate subVI, FreqtoPulse, converts the desired frequency and duty cycle for a PWM output channel to a low time and high time represented in ticks. 

The while loop will execute at a rate defined by the Wait Until Next ms Multiple function.  In this case, the user has defined the wait as 100 ms.  This means that the while loop will execute every 100 ms, or at a rate of 10 Hz. 

3.      Close the FPGA Reference

Figure 9: Final Part of the Host Code

The final part of the Host VI closes the reference to the R Series board.  It also handles any errors that occurred during the execution of the Host VI. 

Front Panel

The Host code Front Panel layout is in a quadrant form.  PWM is on the left, DIO is on the right, Outputs are on the top, and Inputs are on the bottom.    The front panel is shown below:

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Figure 10: Front Panel of the LabVIEW Host Code

Conclusion

This example personality was designed for high channel count PWM.  To use this personality, LabVIEW FPGA is not necessary.  However, any modifications to the FPGA code must be done with LabVIEW FPGA.  The NI-RIO driver is the only driver necessary to use this example personality.

Download the Pulse Width Modulation Example DAQ Personality

Customize Your DAQ Device

National Instruments LabVIEW FPGA Module

R Series Intelligent DAQ Devices

 What Can I Do With LabVIEW FPGA?     

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