Multirate Analog Output Example DAQ Personality

This document is part of the Customize Your DAQ Device series. This FPGA personality allows the use of all 8 analog outputs on R Series PCI and PXI-7833R boards. Each analog output channel can be used in either streaming mode or regeneration mode. Streaming mode means that new samples are continuously sent from the host VI to the FPGA and are output as they are received. Regeneration mode means that a block of memory on the FPGA is filled with samples, and then the FPGA continuously indexes through these samples without further host interaction. Currently, no DAQ board allows the analog outputs to update at independent rates, and this example personality fills that need.

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LabVIEW FPGA Personality

Note: only the PCI and PXI-7833R, which have 3 million gate arrays, can run this personality.

The LabVIEW FPGA code has two main parts:

DMA processing loops

Channel processing loops

1) The DMA processing loops redirect the data that is sent from the host via the DMA FIFOs. Based on whether the user has selected streaming (default) or regeneration mode, the samples will be directed to either a local FIFO or to a memory location, respectively, for a particular channel.

All R Series Intelligent DAQ devices have three DMA channels. This example personality uses three corresponding while loops to process the data and redirect the samples. Several channels share each DMA FIFO and all channels within the group update at the same rate; that is, there can be three different rates among all 8 channels.

The front panel controls Rate012, Rate345 and Rate67 are the number of ticks (using the 40 MHz onboard clock) that the particular group of channels will use as a period. As an example, if Rate012 is equal to 40,000 then channels 0, 1 and 2 will update at 10 KHz (40,000,000/40,000).

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Figure 1: FPGA front panel

The format for sending data over the DMA FIFO is as follows:

Channels 0, 1 and 2 use DMA Output FIFO 0. Channels 3, 4 and 5 use DMA Output FIFO 1. Channels 6 and 7 use DMA Output FIFO 2. Data sent over incorrect DMA FIFOs is discarded.

Elements are sent over the DMA FIFO as a series of elements:

• The first element in the series determines the channel (0-7).
• The second element in the series determines the number of analog output samples in this series.
• The remaining elements are the analog output samples

All of the DMA FIFOs on the FPGA have 4095 elements of type U32.

The DMA Processing loops use a case structure for determining which channel is to receive the remaining samples and a For loop for iterating through them. If the channel is in regeneration mode, then the number of samples is written to location 0 of the memory block for that channel.

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Figure 2: DMA processing loop in regeneration mode

If the channel is in streaming mode, then the number of samples is written to the local FIFO for that channel.

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Figure 3: DMA processing loop in streaming mode

2) The Channel Processing loops are responsible for writing the samples from either the local FIFO or the memory block to the analog output channel. As there are 8 channels, there are 8 while loops, each responsible for one channel. There are two Boolean controls that modify the behavior of a given channel: Pause and Mode.

If a user has selected to pause the channel by setting the Pause control to true, then nothing will be written to that analog output channel and new samples received over the local FIFO are discarded. This prevents the DMA FIFO from getting backed up by a single paused channel. Pausing can be toggled dynamically at run-time.

If the user has set the Mode control to false, then the channel is in streaming mode. In this case, the samples are taken from the local FIFO for that channel and written to the analog output channel. If no samples are available in the FIFO, then the loop continues, and writes out the last value that it did receive. This functionality is obtained by wiring a numeric constant with value 0 into the FIFO read.

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Figure 4: Channel processing loop in streaming mode

If the user has set the Mode control to true, then the channel is in regeneration mode. In this case, the processing loop for that channel will iterate through the memory block rather than the local FIFO. It compares a numeric index against the value in address 0 of the memory block (the total number of samples) and increases by 1 if they do not match. If they do match, then this channel processing loop has reached the end of the regeneration buffer and therefore the index is reset to address 1 and the process continues.

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Figure 5: Channel processing loop in regeneration mode

A local variable is made from Rate012, Rate345 and Rate67 for use in timing the other while loops.

Regeneration can be toggled at run-time; however, it is possible that upon switching back to streaming mode there still be some older samples in the local FIFO. For this reason it is recommended that at the start of the host program, the user decides whether to specify a mode for each channel and not change it at run-time.

As there is 160KB of memory available on the PCI and PXI-7833 R series boards, some channels have been allocated larger memory blocks than others (as likely, not all of them will be used in regeneration mode). The sizes of the memory buffers are:

This allocation was chosen to allow three channels with different update rates (channels 0, 3 and 6) to have sizeable memory block sizes for regeneration. However, with the LabVIEW FPGA module, these sizes could be changed if desired. Also, keep in mind that the very first element is used to store the number of samples in the waveform that are currently stored in the memory block.

LabVIEW Host VI

We have included two example host VIs: one with all channels in streaming mode, and the other with all channels in regeneration mode. However, customized host VIs could easily be written to interface with this FPGA personality, with any mix of channels in regeneration or streaming mode.

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Figure 6: Example host VI front panel

The host code needs to accomplish the following:

1. Open a reference to the FPGA Personality bit file, ensure that the VISA Resource correctly targets your PCI or PXI-7833R and download the bitfile.
2. Configure the depth of the FIFOs, start them, and then run the bitfile. It is recommended that you leave these settings as configured.
3. Write to the controls on the FPGA’s front panel for each channel; namely:
   1. Pause
   2. Mode
   3. Update Rate 
4. Send series of elements over the correct DMA FIFO for each channel. This will need to be done repeatedly if in streaming mode, but only once if the channel is in regeneration mode. The host is responsible for writing a number of samples to the memory block that is less than or equal to its size. The host VI can replace the waveform in the memory block at run-time by ensuring the Mode control is true and sending another series of elements across the proper DMA FIFO for that channel.
5. Close the FPGA reference. If the system is in streaming mode, “Close and reset” should be selected as an option for this function, as no more samples will need to be written. However, if there are any channels in regeneration mode, and the user wishes to have them continue writing even after the host VI has stopped, then “Close” should be selected and no resetting should be done.

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Figure 7: Initializing the FPGA section of the host VI

In this snippet of block diagram code from the example regeneration host VI, we open an FPGA reference, download the bitfile to the FPGA, and configure the depth of the local DMA FIFOs (those which will be on the host PC). We then start the DMA FIFOs and run the bitfile. Also, not shown in this screenshot, we set the update rate of the channels. The user will specify the update rate in terms of frequency, but the FPGA code is expecting this in terms of number of ticks of the 40 Mhz clock, so we use the "ToTicks.vi" subVI.
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Figure 8: Writing samples from Channels 0, 1 and 2 to their corresponding DMA FIFO

In this section of block diagram code, from the example streaming host VI, we iterate through the channels to create samples using the basic function generator VI, write the samples to their respective DMA FIFO, and check if the user has paused any of the channels (top-right). Previous to this in the block diagram, we set which of the channels are in regeneration mode.

We have written the example host using three parallel while loops, so that it can supply the three DMA channels with data at different rates. This prevents starvation of higher update rate channels. When high update rates are used, you may need to increase the number of elements sent in each DMA transfer.

Conclusion

This example personality was designed to allow very flexible configurations of analog output. It can be run as-is for a multirate analog output functionality or used as a starting point for more specialized test or control applications.

To use this personality, LabVIEW FPGA is not necessary.  However, any modifications to the FPGA code must be done with LabVIEW FPGA.  The NI-RIO driver is the only driver necessary to use this example personality

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