High Channel High Performance Multi-Chassis System

The high channel high performance multi-chassis system is the main architecture for high channel count (up to 51 chassis/ 13000 channels) and high data rates (204.8 kS/s/ch and below). The dedicated CPU per chassis provides more bandwidth for streaming data to disk. This is because each PXI-1045 filled with DSA cards has a dedicated CPU w/ external or internal RAID HardDrive(s) for storage.

Click here to download the code for this system

Architecture

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Master CPU

This layout is based on the master-slave architecture.  The Master CPU is acting controller of this layout.  It is in direct communication with the timing chassis, via MXI-Express, which is used to synchronize all chassis together.  This in turn provides very low phase mismatch between channels in different chassis.  The Master CPU also communicates with the Slave CPUs, via TCP/IP.  This allows the Master CPU to send commands to the slave CPUs such as starting or stopping all acquisitions simultaneously. 

Slave CPUs

The slave CPUs are directly connected individually to a single DSA chassis, via MXI-Express.  These slave CPUs, while being controlled by a master chassis, are in control of their respective DSA chassis.  The slave CPU’s function is to start acquisition of its corresponding DSA chassis in sync with the Main CPUs commands and provide the HardDrive for data storage. 

PXI-44xx

The architecture shown above is configured for PXI-44xx.  This is because there are multiple DSA boards that can be used in this architecture depending on the desired performance and cost.  Here is a description of each board:

PXI-4498 Specifications (Highest Channel Density)

• 16 simultaneously sampled analog inputs at up to 204.8 kS/s
• 24-bit resolution ADCs with 114 dB dynamic range
• 4 gain settings up to +30 dB for input ranges from ±316 mV to 10 V
• Software-configurable 4 mA IEPE and TEDS for microphones and accelerometers
• Variable antialiasing filters
• AC-coupled analog inputs at 0.5 Hz

PXI-4462 Specifications (Highest Performance)

• Six gain settings for input ranges from ±316 mV to 42.4 V
• Four simultaneously sampled analog inputs at up to 204.8 kS/s
• Software-configurable AC/DC coupling and IEPE conditioning
• Variable antialiasing filters
• Support for IEEE 1451.4 Class 1 Smart (TEDS) Sensors
• 24-bit resolution ADCs with 118 dB dynamic range

PXI-4472 Specifications (Lowest Cost)

• ±10 V input range or ±31 V with SMB-120 cable
• Ability to synchronize up to 5,000 channels in a PXI system
• Eight simultaneously sampled analog inputs at up to 102.4 kS/s
• Software-configurable AC/DC coupling and IEPE conditioning
• Variable antialiasing filters
• 24-bit resolution ADCs with 110 dB dynamic range

** It is important to note that the PXI-447x series cannot be used past slot 15 in a PXI-1045.  This is because the PXI-447x series uses the star trigger line for synchronization and is not capable of PLLing to the PXI-Clk10 like the PXI-449x and PXI-446x series.    

Code Template

The above architecture is a working solution for many noise mapping users that require high channel count and high sampling rates.  The architecture and necessary hardware is clearly laid out above.  The software to handle the synchronization of these multiple CPUs and their chassis and stream data to disk is included with this tutorial.  The following paragraphs give a brief overview of the code that has been developed for this architecture. 

Project

The zip file that is referenced for download in this tutorial contains a LabVIEW 8.2 project and the necessary VIs for running the software.  Here is a look at the opened project file:                        

Within this project, there are 3 folders.  The first folder is titled “446x/9x”.  Within this folder lies the code for the above architecture if PXI-446x or PXI-449x DSA boards are used.  The second folder is titled “447x”.  Within this folder lies the code for the above architecture if PXI-447x DSA boards are used.  Finally, the third folder contains the necessary subVIs for these top level VIs. 

Master CPU

Depending upon which DSA boards are used, the corresponding master VI should be opened on the master CPU.  The front panel of the master VI is shown below:

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To configure the VI for data acquisition:

1. Fill in the “Array of Master 665x Resource Names” array with the device identifiers for all master 665x devices in the master timing chassis.
2. Fill in the “Slaves IP Address” array with the IP addresses of all Slave CPUs in the architecture.
3. Run the VI after starting all slave VIs on the slave CPUs.
4. Press the “Stop” button to terminate acquisition on all chassis and stop the VI.

The function of this VI is as follows:

1. Establish communication with the Slave CPUs listed in the “Slaves IP address” string array control.
2. Initialize the master timing chassis connected to the master CPU.
3. Start Acquisition on all boards simultaneously.
4. Stop acquisition on all boards simultaneously.
5. Close TCP/IP communication.

Slave CPU

Depending upon which DSA boards are used, the corresponding slave VI should be opened on the slave CPUs.  The front panel of the slave VI is shown below:

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To configure the VI for data acquisition:

1. Fill in the “Slave 6651 Visa Resource Name” string control with the device identifier for the 6651 in the chassis connected to the slave CPU.
2. Fill in the “File Path” control with the desired path and name of the file for which the data acquired by the corresponding chassis will be written to.
3. Fill in the “Physical Channels” control with the
4. Specify desired “Sample Rate” and “Samples to Read”.
5. Start all slave CPU VIs before starting the master CPU VI. 

The function of this VI is as follows:

1. Establish communication with the master CPU.
2. Initialize the slave timing device in the chassis connected to the slave CPU.
3. Configure a data acquisition task for the DSA boards in the chassis.
4. Open a file for streaming the acquired data to disk.
5. Begin acquiring data and writing to file upon start pulse sent by master timing chassis.
6. Stop acquisition, close file, and end TCP/IP communication upon command from master CPU.

MAX Configuration

For every chassis configured in this system, PXI_Trig0, PXI_Trig4, and PXI_Trig5 must be routed "Away From Slot 1".  This is shown in below:

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Related Links

Click here to download the code for this system

DSA Main Portal                       

Streaming Page

DSA Page

http://www.ni.com/soundandvibration/

 

 

 

 

            

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