High Channel Medium Performance Multi-Chassis System

The high channel medium performance multi-chassis system is the main architecture for systems with a high channel count (up to 13 chassis/ 3300 channels) and medium data rates. This system has a single dedicated CPU for all chassis to stream data to. This results in lower cost and easier code architecture, but also results in lower acquisition rates.

Click here to download the code for this system

Architecture

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CPU

A single CPU controls this entire layout.  It uses MXI-Express to collect data from the DSA chassis and stream it to a RAID0 array.  The CPU also controls timing and synchronization of the DSA chassis through a timing chassis connected via MXI-Express.

MXI Chassis

Each MXI chassis uses a MXI-Express module in the first slot to interface with a PCIe-8362 MXI controller connected to the CPU.  The remaining slots in the chassis are used for additional MXI-Express modules that are connected to each DSA chassis.  Each 8-slot PXI-1042 chassis can stream data from up to 7 DSA chassis, although one slot of one MXI chassis must be used to communicate with the timing chassis.

Timing (Master) Chassis

This PXI-1042 chassis contains one MXI-Express module in the first slot for communication with the MXI chassis and CPU.  The rest of the slots contain PXI-6653 timing and synchronization modules.  Each of these modules is capable of synchronizing up to 3 DSA chassis.

DSA (Slave) Chassis

These 18-slot PXI-1045 chassis contain the hardware that actually acquires the signals.  Each chassis has an MXI-Express module for streaming data to the CPU and a PXI-6651 module to control timing and synchronization.  In this example configuration, the remaining sixteen slots are filled with PXI-44xx dynamic signal acquisition modules.

PXI-44xx

The architecture shown above is configured for PXI-44xx.  This is because there are multiple DSA boards that can be used in this architecture depending on the desired performance and cost.  Here is a description of each board:

PXI-4498 Specifications (Highest Channel Density)

• 16 simultaneously sampled analog inputs at up to 204.8 kS/s
• 24-bit resolution ADCs with 114 dB dynamic range
• 4 gain settings up to +30 dB for input ranges from ±316 mV to 10 V
• Software-configurable 4 mA IEPE and TEDS for microphones and accelerometers
• Variable antialiasing filters
• AC-coupled analog inputs at 0.5 Hz

PXI-4462 Specifications (Highest Performance)

• Six gain settings for input ranges from ±316 mV to 42.4 V
• Four simultaneously sampled analog inputs at up to 204.8 kS/s
• Software-configurable AC/DC coupling and IEPE conditioning
• Variable antialiasing filters
• Support for IEEE 1451.4 Class 1 Smart (TEDS) Sensors
• 24-bit resolution ADCs with 118 dB dynamic range

PXI-4472 Specifications (Lowest Cost)

• ±10 V input range or ±31 V with SMB-120 cable
• Ability to synchronize up to 5,000 channels in a PXI system
• Eight simultaneously sampled analog inputs at up to 102.4 kS/s
• Software-configurable AC/DC coupling and IEPE conditioning
• Variable antialiasing filters
• 24-bit resolution ADCs with 110 dB dynamic range

** It is important to note that the PXI-447x series cannot be used past slot 15 in a PXI-1045.  This is because the PXI-447x series uses the star trigger line for synchronization and is not capable of PLLing to the PXI-Clk10 like the PXI-449x and PXI-446x series.    

Code Template

The above architecture is a working hardware solution for many noise mapping users that require medium sampling rates.  The software to handle synchronization, timing, and data streaming to disk is included with this tutorial and described below. 

Project

The zip file attached to this tutorial contains a LabVIEW 8.2 project and the necessary VIs for running the software.  Here is a look at the structure of the project file:

                        

Within this project, there are four folders.  The first two folders contain the LabVIEW code for the CPU.  Only one of these VIs is actually used, depending on whether PXI-446x/9x or PXI-447x hardware is being used.  The “SubVIs” folder contains the SubVIs necessary for the main VIs to function.  Finally, the “Documentation” folder contains additional information about the performance of this architecture.      

Front Panel

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To configure the VI for data acquisition:

1. Fill in the “Array of Master 665x Resource Names” array with the device identifiers for each of the master 665x modules in the timing chassis.
2. Fill in the “Array of Slave 665x Resource Names” array with the device identifiers for each of the slave 665x modules in the DSA chassis.
3. Enter the slot number of each DSA module in the “PXI Slots of DSA devices in slaves” array.
4. Select which physical channels to record in the “Physical Channels” field.
5. Set a sampling rate and number of samples.
6. Click the Run arrow to begin acquisition and streaming.
7. Press the “Stop” button to terminate acquisition on all chassis and stop the VI. 

The function of this VI is as follows:

1. Configures the sample clock, sync pulse, and start trigger on the timing chassis.
2. Configures each slave chassis to receive their sample clock, sync pulse, and start trigger from the timing chassis.
3. Issues an initial sync pulse to synchronize all of the devices.
4. Issues a start trigger to begin data acquisition.
5. Acquires data and streams it to disk.
6. Stops data acquisition and close the task.

MAX Configuration

For every chassis configured in this system, PXI_Trig0, PXI_Trig4, and PXI_Trig5 must be routed "Away From Slot 1".  This is shown in below:

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Related Links

Click here to download the code for this system

DSA Main Portal                       

Streaming Page

DSA Page

http://www.ni.com/soundandvibration/

 

    

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