Medium Channel Low Cost Multi-Chassis System

The medium channel low cost multi-chassis system is the main architecture for systems with low channel count (up to 3 chassis/ 570 channels) and medium data rates. This architecture provides the most cost savings in comparison with the other high channel multi-chassis systems.

Click here to download the code for this system

Architecture

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CPU

A single CPU controls this entire layout.  It uses MXI-Express to communicate with a single chassis acting as the controller chassis.  The controller chassis contains: timing for the other DSA chassis, MXI-Express cards to communicate with the other DSA chassis, and five DSA boards to take full advantage of space. 

DSA Chassis

These 18-slot PXI-1045 chassis contain the hardware that actually acquires the signals.  Each chassis has a MXI-Express module for streaming data to the CPU and a PXI-6651 module to control timing and synchronization.  In this example configuration, the remaining sixteen slots are filled with PXI-44xx dynamic signal acquisition modules.

PXI-44xx

The architecture shown above is configured for PXI-44xx.  This is because there are multiple DSA boards that can be used in this architecture depending on the desired performance and cost.  Here is a description of each board:

PXI-4498 Specifications (Highest Channel Density)

• 16 simultaneously sampled analog inputs at up to 204.8 kS/s
• 24-bit resolution ADCs with 114 dB dynamic range
• 4 gain settings up to +30 dB for input ranges from ±316 mV to 10 V
• Software-configurable 4 mA IEPE and TEDS for microphones and accelerometers
• Variable antialiasing filters
• AC-coupled analog inputs at 0.5 Hz

PXI-4462 Specifications (Highest Performance)

• Six gain settings for input ranges from ±316 mV to 42.4 V
• Four simultaneously sampled analog inputs at up to 204.8 kS/s
• Software-configurable AC/DC coupling and IEPE conditioning
• Variable antialiasing filters
• Support for IEEE 1451.4 Class 1 Smart (TEDS) Sensors
• 24-bit resolution ADCs with 118 dB dynamic range

PXI-4472 Specifications (Lowest Cost)

• ±10 V input range or ±31 V with SMB-120 cable
• Ability to synchronize up to 5,000 channels in a PXI system
• Eight simultaneously sampled analog inputs at up to 102.4 kS/s
• Software-configurable AC/DC coupling and IEPE conditioning
• Variable antialiasing filters
• 24-bit resolution ADCs with 110 dB dynamic range

** It is important to note that the PXI-447x series cannot be used past slot 15 in a PXI-1045.  This is because the PXI-447x series uses the star trigger line for synchronization and is not capable of PLLing to the PXI-Clk10 like the PXI-449x and PXI-446x series.    

Code Template

The above architecture is a working solution for many noise mapping users that require medium sampling rates.  The architecture and necessary hardware is clearly laid out above.  The software to handle the synchronization of these multiple CPUs and their chassis and stream data to disk is included with this tutorial.  The following paragraphs give a brief overview of the code that has been developed for this architecture. 

Project

The zip file that is referenced for download in this tutorial contains a LabVIEW 8.2 project and the necessary VIs for running the software.  Here is a look at the opened project file:

                           

FrontPanel

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To configure the VI for data acquisition:

1. Fill in the “Master 6653 Visa Resource Name" and "Slave 6653 Visa Resource Names."
2. Fill in the “Physical Channels" control with all channels being acquired from. 
3. Fill in the Sampling Rate and Samples to Read.
4. Run the VI
5. Press the “Stop” button to terminate acquisition.

The function of this VI is as follows:

1. Configures the sample clock, sync pulse, and start trigger on the timing chassis.
2. Configures each slave chassis to receive their sample clock, sync pulse, and start trigger from the timing chassis.
3. Issues an initial sync pulse to synchronize all of the devices.
4. Issues a start trigger to begin data acquisition.
5. Acquires data and streams it to disk.
6. Stops data acquisition and close the task.

MAX Configuration

For every chassis configured in this system, PXI_Trig0, PXI_Trig4, and PXI_Trig5 must be routed "Away From Slot 1".  This is shown in below:

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Related Links

Click here to download the code for this system

DSA Main Portal                       

Streaming Page

DSA Page

http://www.ni.com/soundandvibration/ 

      

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