Exercise 2: Create an FPGA Project and Application

This demo will show how to use the FPGA Project Wizard in the LabVIEW 8.5 FPGA Module to jump-start the design of an intelligent DAQ device. This demo may be used with any FPGA target. This demo script will use a simulated CompactRIO target. This tutorial will walk through using the FPGA Project Wizard to create a LabVIEW Project and then using the FPGA Wizard to generate LabVIEW code for I/O and communication.

FPGA Hardware Setup

1. To launch the FPGA Project Wizard, select FPGA Project from the Targets drop down menu on the LabVIEW Getting Started Window and click Go.

2. In the FPGA Project Wizard dialog box, select CompactRIO Reconfigurable Embedded System as the desired project type.  Click Next > to proceed.

3. In the next window, you have two options.  The Discover existing system option automatically detects a connected FPGA target and all connected modules.  If we actually had a CompactRIO or other FPGA target connected to this machine, you could select the Discover existing system option.  Because we don’t have an FPGA target connected to the online evaluation, you will have to select a target and modules manually.  Select the Create new system radio button and click Next  >.
4. For this exercise, we will build the following system:

CompactRIO Simulated System

• cRIO 9014 Real-Time Controller
• cRIO 9103 FPGA Backplane
• NI 9215 4-Channel Simultaneous Analog Input
• NI 9263 4-Channel Analog Output
• NI 9411 6-Channel Digital Input
• NI 9474 8-Channel High Speed Digital Output

5. The next dialog box generates a preview of a LabVIEW project with your CompactRIO Real-Time target, FPGA target, and all the C Series I/O modules configured.  Make sure the Launch FPGA Wizard when finished check box is checked.  In the next steps, the FPGA Wizard will automatically generate LabVIEW FPGA (Target) and LabVIEW Real-Time (Host) code in a practical architecture to get you started in your embedded system development.  Click Finish to create the LabVIEW Project and launch the FPGA Wizard.

FPGA Wizard

You can use the FPGA Wizard to design and generate LabVIEW code for intelligent data acquisition and process-control applications.  The wizard provides a starting point for FPGA development by creating common architectures to generate code specific to your hardware.  Code generated by the FPGA Wizard can be run as is, or you can further customize it to meet your specific measurement or control needs.

6. Click on the Add Item menu and select Timing Engines>>Buffered DMA Input.
7. In the dialog, change the name to “Data Aquistion” and change the rate to 50k.
8. Click on the Add Item menu and notice that you can select Analog or Digital Inputs as possible input tasks for the Buffered DMA Input timing engine.
9. Select an AI function.  You configured Mod1 as an NI 9215 in the FPGA Project Wizard, so ensure that Mod1/AI0 is selected as the Analog Input Resource.  Notice that you can select Use Engineering Units.  Selecting this option will generate code on the host to convert binary values returned from the FPGA into Volts. 

There are some tasks that don’t necessarily need user-defined timing and synchronization with the host.  An example is a counter or Quadrature encoder – with each of these, the faster you can run the counter clock, the higher the counter’s precision.  Additionally, you only need the latest value in time, so synchronizing the acquisition with the host is not necessary.  Also since the code you are creating will run on an FPGA, all timing engines will run independently and in parallel.  We will now create an edge counter.

10. Click on the Add Item menu and select Timing Engines>>Single Point Continuous
11. Name this timing engine “continuous loop”
12. Add an Edge Counter function.  The default settings for this function indicate that it will use digital input line on the NI 9411 C Series Module, and it will count rising edges. 
13. Add a Quadrature Counter function.  The default settings for this function indicate that it will use two digital input lines on the NI 9401 module. The FPGA Wizard should appear as seen below.

14. Click on Save to save your configuration.  You can save the FPGA Wizard configuration for use later. 
15. Click on Generate Code – the window below should appear.  You can use this window to change the name and location of the code that will be generated.

16. Clock on OK to generate code.  This may take a few minutes.  On a laptop with an Intel® Core™2 - 2.0GHz processor, this took about 2 minutes. Code generation is not instantaneous because LabVIEW is actually scripting through steps to generate code the same way you would do manually.  A couple minutes is actually must faster than it would take for someone to program an FPGA and host VI manually.
17. Once complete, a dialog will appear stating that code generation was successful and the new VI’s were placed in the LabVIEW project.  Click OK.

18. Exit the FPGA Wizard by clicking Close.
19. You should now investigate the code that was automatically generated by LabVIEW.  Open the MyFPGACode.vi and open the block diagram.  You can find MyFPGACode.vi in the LabVIEW project, nested under RT CompactRIO Target>>FPGA Target>>MyFPGACode.lvlib.
20. The FPGA Wizard not only makes development easier, but it can also show you some best practices when implementing intelligent DAQ capabilities.  Also, code generated by the FPGA Wizard contains comments so you can understand why code was generated the way it was.  We will look through the functionality of each loop.
    1. Data Acquistion (top loop): This loop initializes while it waits for a software start trigger.  Then it sets the sample rate, performs Analog Input writes data to a DMA FIFO to transfer it to the host.  The loop also performs error and lateness checking to report data over and underflows to the buffer.
    2.  Continuous Loop (second loop from the top):  This loop exchanges data with the host for all of the non-timed I/O (i.e. the edge counter and quadrature encoder).  Notice that loop only handles data transfer for these functions.  The actual functions are placed in their own parallel loops. 
    3. Counter and Quadrature Encoder Loops (two bottom loops):  These loops implement the counter and quadrature encoder functions using single-cycle timed loops and high-level IP blocks.  These blocks make implementing these functions much easier and modular.  You can take these VIs and implement them directly in your application.  Data is passed from these loops to the Continuous Loop via local variables.

Conclusions:  You have now created a LabVIEW FPGA application that acquires analog data continuously, performs duties of an edge counter, and decodes quadrature encoder measurements.  This was all done in a matter of minutes.  This application is functional as is, or you could add any additional custom design you would like.  The FPGA wizard creates code that is scalable and commented so you can quickly pick up where it leaves off and customize your designs.  In the context of the Online Evaluation Environment, this code could be compiled, but not run, as there is no physical target to run the FPGA code on.  If you had your own CompactRIO, you could start compiling and minutes later, you would have a working application. 

Feel free to also open and investigate the Real-Time host VI that the FPGA wizard generated as well.  The host VI is also added to the project, nested under RT CompactRIO Target>>MyHostCode.lvlib.  The wizard created code that communicates with the FPGA, acting as a user interface for the analog input, edge counter, and quadrature encoder measurements.  The host VI will open with a broken run arrow because it cannot be run until the FPGA VI is compiled and a physical target is selected in the project.

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Helpful in a Time of Need
I found this article very helpful in a pinch. I was under time const
- Dec 1, 2008

Helpful in a Time of Need
I found this article very helpful in a pinch. I was under time constraint to teach myself FPGA coding in LabVIEW over the weekend (Thanksgiving weekend - yuck). It might be good to note that the "Launch FPGA Wizard when finished" checkbox does not appear if you do not have NI-RIO installed. (This is on the Device Drivers disk.) I didn't have it installed, and it took me a couple of hours to figure out why I didn't see that checkbox. Another related article that desperate coders might find helful is" LabVIEW FPGA Module:" Traininghttp://zone.ni.com/devzone/cda/tu t/p/id/3555#toc0
- Darell Newton, Agile Engineering. dnewton@agileeng.com - Dec 1, 2008

update needed
this needs updating to refelect the automatic detection of C-Series modules.
- Evan Robinson, National Instruments. evan.robinson@ni.com - Jul 29, 2008