Quadrature Encoder Example DAQ Personality

This document is part of the Customize Your DAQ Device series. This document specifically describes the Quadrature Encoder example personality. The quadrature encoder personality was designed to target high channel count needs for both quadrature encoder output and input. This personality has 8 quadrature encoder channels configurable for input or output. The attached host example configures it for 6 quadrature encoder inputs and 2 quadrature encoder outputs.

Download the Quadrature Encoder Example DAQ Personality.

LabVIEW FPGA Personality

The LabVIEW FPGA code is the portion of this code embedded on the R Series  board.  This code defines the FPGA in the same way an ASIC defines a MultifunctionDAQ board.  This code was written with LabVIEW FPGA and compiled into a bitfile.  It is in its finalized form and does not require LabVIEW FPGA to be used.  However, to customize this code LabVIEW FPGA is required. 

This LabVIEW FPGA personality implements the Single Cycle Timed Loop (SCTL) architecture, with each SCTL dedicated to specific DIO lines.  Here is a look at the Block Diagram for the LabVIEW FPGA code:

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Figure 1: Block Diagram of the LabVIEW FPGA code

Quadrature Encoder

Each SCTL on the block diagram is dedicated to a particular set of DIO lines and has the flexibility to perform quadrature encoder output or input.  This functionality is defined by a simple case structure and Boolean control.  If the Boolean is set to a false value, the DIO lines will be used for quadrature encoder output.  If the Boolean is set to a true value, the DIO lines will be used for quadrature encoder input.  These two cases are shown below:

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 Figure 2: Single Cycle Timed Loop Dedicated to DIO Lines 0 thru 2 (Both cases)

Quadrature Encoder Input

For quadrature encoder input, three digital lines are monitored at the rate of the FPGA clock (it is 40 MHz in this case).  These three digital lines are the A, B, and Z quadrature encoder inputs.  These digital lines and the algorithm for determining position are shown below. 

 

Figure 3: Quadrature Encoder Input Logic (contained in a subVI)

Quadrature Encoder Output

For quadrature encoder output, the FPGA code is also run at the rate of the FPGA clock.  The user specifies the direction and rate for the quadrature encoder ouput.  The quadrature encoder output algorithm is shown below. 

Figure 4: PWM Output Logic (contained in a subVI) 

Digital IO

The LabVIEW FPGA architecture makes it simple to add additional loops in parallel without affecting other parts of the FPGA application.  For this reason, the LabVIEW FPGA code also takes advantage of the remaining DIO lines by configuring all of Connector 1 as static digital outputs and all of Connector 2 as static digital inputs.  This FPGA code is shown below:

Figure 5: Static DIO Logic

LabVIEW Host Personality

The LabVIEW Host code acts as the User Interface used to communicate with the FPGA.  The Host code interacts directly with the FPGA code by updating controls and reading from indicators on the Front Panel of the FPGA code.  This functionality is supported by the NI-RIO driver. 

This example personality consists of three main portions:

1.      Open a reference to the FPGA bitfile on the target R Series board.

2.      Use a Read/Write Node to update controls and indicators on the FPGA Front Panel.

3.      Close the reference to the FPGA bitfile.

Block Diagram

Here is a look at the example Host Block Diagram:

Figure 6:  Block Diagram of the LabVIEW Host Code

These three main steps outlined above describe the overall setup of the Host VI.  This Host code is a little more complex because of conversions that must take place prior to writing to a control.  The following sections are going to explain these three main steps in more detail:

1.      Open Reference to Target FPGA

Figure 7: First Part of the Host Code

The first part of the code is the initialization stage.  In this part of the code, the resource name for the target R Series board is passed to the Open FPGA VI Reference.  This function opens a reference to the board that can be used by any subsequent functions or subVIs that communicate with the FPGA.  The reference is then passed to the Read/ Write Node and the digital lines are initalized to function as an output or input. 

2.      Read FPGA Indicators and Write to FPGA Controls

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Figure 8: Middle Part of the Host Code

The middle part of the code will consume the majority of the execution time for this Host VI.  This part of the code consists of a while loop with a Read/ Write node inside of it.  The Read/ Write node allows users to write to controls and read from indicators on the front panel of the FPGA code.  In the figure shown above, each input to the node is a control in the FPGA code. 

For example, “Reset - Quad 0” is the name of a control in the FPGA code.  This particular control resets the quadrature encoder position count stored on the FPGA.  The corresponding indicator "Encoder Position - Quad 0" returns the current quadrature encoder position tha tis stored on the FPGA.

LabVIEW FPGA only supports integer math and integer data-types.  For this reason, any data returned from the FPGA to the Host code will be a U32.  For that reason, there is an intermediate subVI called "Ticks to Deg" to convert the U32 to a double data type in degrees.   

The while loop will execute at a rate defined by the Wait Until Next ms Multiple function.  In this case, the user has defined the wait as 100 ms.  This means that the while loop will execute every 100 ms, or at a rate of 10 Hz. 

3.      Close the FPGA Reference

Figure 9: Final Part of the Host Code

The final part of the Host VI closes the reference to the R Series board.  It also handles any errors that occurred during the execution of the Host VI. 

Front Panel

The Host code Front Panel layout is in a quadrant form.  Quadrature encoder is on the left, DIO is on the right, Inputs are on the top, and Outputs are on the bottom.    The front panel is shown below:

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Figure 10: Front Panel of the LabVIEW Host Code

Conclusion

This example personality was designed for high channel count quadrature encoder.  To use this personality, LabVIEW FPGA is not necessary.  However, any modifications to the FPGA code must be done with LabVIEW FPGA.  The NI-RIO driver is the only driver necessary to use this example personality.

Download the Quadrature Encoder Example DAQ Personality

Customize Your DAQ Device

National Instruments LabVIEW FPGA Module

R Series Intelligent DAQ Devices

 What Can I Do With LabVIEW FPGA?     

             

Reader Comments | Submit a comment »

Figure 3 exhibits appears to suffer from a race condition flaw. The 'Source A' value could be written to the 'A Register' indicator before 'A Register' local variable is read. If this happens, a quad state change can be missed. Ditto for 'B Register'. Caveat: I don't use FPGA module, comment based on typical LabVIEW sequencing and parallelism rules. -Kevin P.
- Oct 5, 2007