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Welcome to the LabVIEW FPGA Module Training Course for the Xilinx Spartan 3E hardware. This free training material is divided into lessons. Below you will see the outline for each section. Some lessons include a Word document with exercise instructions and a file containing LabVIEW VIs with exercise solutions. Previous knowledge of LabVIEW is highly recommended. This training material is preliiminary and will change as new revisions become available. DOWNLOAD: To download the Xilinx Spartan 3E plug-in driver, visit www.ni.com/info Enter the information word spartan3e Note- This driver is for Academic teaching use only and includes special licensing provisions.
Table of Contents
- Lesson 1 - Understanding Embedded Design Methods
- Lesson 2 - LabVIEW FPGA Programming Techniques
- Lesson 3 - FPGA I/O
- Lesson 4 - FPGA Timing
- Lesson 5 - Host PC Communication with Running LabVIEW FPGA Code
- Lesson 6 - Advanced Host Based Communication and Control
- Lesson 7 - Optimizing Speed and Timing of LabVIEW FPGA Code
- Lesson 8 - Linking Existing VHDL Code from WebPACK into LabVIEW FPGA
Lesson 1 - Understanding Embedded Design Methods
General Overview of Embedded Design Trends
Lesson 2 - LabVIEW FPGA Programming Techniques
Getting Started Exercise using NI R-Series Hardware,
Configuring hardware, and creating a new Project
exercise_2.1_NI_R_Series.doc
Getting Started Exercise using Spartan 3E Hardware
Configuring hardware and opening example Project
exercise_2.1_Spartan_3E.doc
Lesson 3 - FPGA I/O
Creating a new Spartan 3E Project
exercise_3_Spartan_3E.doc
Digital communication methods with LabVIEW FPGA
exercise_3A.doc
Lesson 4 - FPGA Timing
Custom triggering with LabVIEW FPGA
exercise_4.1_NI_R_Series.doc
Data flow in parallel loops using FIFOs
exercise_4.2.doc
Lesson 5 - Host PC Communication with Running LabVIEW FPGA Code
Create host based VI's for LabVIEW FPGA running code
exercise_5.1_NI_R_Series.doc
exercise_5.1_Spartan_3E.doc
Lesson 6 - Advanced Host Based Communication and Control
Interrupt based processing with LabVIEW FPGA
exercise_6.1.doc
Lesson 7 - Optimizing Speed and Timing of LabVIEW FPGA Code
Lesson 8 - Linking Existing VHDL Code from WebPACK into LabVIEW FPGA
Using existing VHDL filter code with LabVIEW FPGA
exercise_8_Spartan_3E.doc
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