LabVIEW FPGA Benchmarks for Virtex-5 R Series Targets

How do the new Virtex-5 R Series targets compare to previous Virtex-II based devices?  This application note presents LabVIEW FPGA benchmarks that have been completed to provide a frame of reference when evaluating the benefits newer FPGA technology.

Introduction:

The newest generation of R Series Intelligent DAQ modules features Virtex-5 FPGA chips for custom triggering and onboard processing capabilities.  The new PXI-7841R and PXI-7851R have a Virtex-5 LX30 FPGA, and the new PXI-7842R and PXI-7852R have a Virtex-5 LX50 FPGA. The number of “system gates” has traditionally been a way to compare FPGA chips to ASIC technology, but does not truly describe the number of individual components inside an FPGA. This is one of the reasons why Xilinx did not specify the number of gates for the new Virtex-5 family.  How then, do the new Virtex-5 R Series targets compare to previous Virtex-II based devices?  In reality, there is no single specification that tells the whole story.  The new Virtex-5 FPGA architecture itself is quite different, and trying to looks at individual specs becomes a comparison of apples and oranges.

The Virtex-5 FPGA architecture is optimized to execute faster and more efficiently using single-cycle timed loops in the LabVIEW FPGA Module. The fundamental building blocks for implementing digital logic inside FPGA chips are called slices, and each slice is composed of flip-flops and look-up tables (LUTs). Previous-generation Virtex-II FPGAs use 4-input LUTs for up to 16 combinations of digital logic values. The new Virtex-5 FPGAs use 6-input LUTs for up to 64 combinations, increasing the amount of logic that you can implement per slice.  The single-cycle timed loop structure in LabVIEW FPGA takes advantage of six-input LUTs for substantially improved resource utilization. This means you can optimize more LabVIEW FPGA code to fit within Virtex-5 FPGAs and perform more operations per clock cycle. In addition, the slices themselves are placed in closer proximity to each other to reduce the propagation delay of electrons and increase overall execution rates.

For more information on understanding specifications and how FPGAs work, read the “FPGAs under the Hood” white paper.

Without having to understand the low-level details of FPGA architectures, we can examine LabVIEW FPGA benchmarks to see examples of how Virtex-5 R Series targets provide bigger and faster FPGAs. 

 

Virtex-5 Benchmarks for Size:

In comparing the size differences between Virtex-II and Virtex-5 FPGAs, we wanted to get a feel for how much LabVIEW code would fit on each target.  Figure 1 shows the piece of graphical code used to benchmark the amount of general logic resources.

 

 

Figure 1. Section of code used for General Logic Benchmarking

We took this code, which primarily uses the logic resources (Flip-Flops and LUTs), and tested to see how many times it would fit on each target.  We used a single-cycle timed loop to make the most of the new 6-input LUTs on Virtex-5 FPGAs.  This piece of code includes IP cores, (or function blocks) for simple event counting, pulse-width modulation and quadrature encoder reading.  These functions do not require any specialty resources like multipliers or embedded block RAM.  This piece of code fit 22 times on a PXI-7831R, which has a Virtex-II 1M gate FPGA.  Figure 2 shows the resulting block diagram, with all code within a single single-cycle timed loop structure.

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Figure 2. LabVIEW FPGA block diagram for a PXI-7831R, with 22 instances of general logic code.

 

Table 1 shows the maximum number of time the benchmarking code fit into four different LabVIEW FPGA targets.

 

LabVIEW FPGA Target	FPGA	Max Number of Benchmark Code Instances
PXI-7831R	Virtex-II 1M Gate	22
PXI-7833R	Virtex-II 1M Gate	63
PXI-7841R	Virtex-5 LX30	45
PXI-7842R	Virtex-5 LX50	70

Table 1:  Maximum number of Benchmark Code instances for each FPGA target

 

Figure 3 shows a chart that takes the same data in Table 1, and directly compares the Virtex-5 LX30 with a 1M Gate Virtex-II FPGA, and the Virtex-5 LX50 with a 3M gate Virtex-II FPGA.

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Figure 3.  Direct size comparison of new Virtex-5 FPGAs with legacy Virtex-II FPGAs

 

Virtex-5 Benchmarks for Speed:

Another important benefit that the new Virtex-5 architecture provides is the ability to compile code at faster rates, increasing the processing capabilities of LabVIEW FPGA hardware. One way to quantify this improvement execution speed is to take a specific piece of code within a single-cycle timed loop and ramp up the clock rate until the compilation process can no longer meet timing requirements.  Figure 4 shows the single-cycle timed loop that was used to compare Virtex-II targets to Virtex-5 targets. 

 

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Figure 4: LabVIEW FPGA block diagram of ten adders, serially configured within a single-cycle timed loop structure.

 

The graphical code within this loop serially adds eleven 8-bit numbers together, using ten adder functions in LabVIEW.  While this is not the most efficient way to add eleven numbers together, we can use this code to assess the relative performance differences between each target and benchmark the maximum clock rates.  Table 2 shows the results of these speed benchmarks.

 

LabVIEW FPGA Target	FPGA	Maximum clock rate For Ten Serial Adders
PXI-7831R	Virtex-II 1M Gate	45MHz
PXI-7833R	Virtex-II 1M Gate	45.22MHz
PXI-7841R	Virtex-5 LX30	90MHz
PXI-7842R	Virtex-5 LX50	87.27MHz

Table 2:  Maximum clock rate of ten serial adders for each FPGA target.

 

As shown in Table 2, these speed benchmarks demonstrate that the new Virtex-5 FPGA architecture is approximately twice as fast as legacy Virtex-II FPGAs.  The chart shown in figure 5 compares the Virtex-II 1M gate FPGA to the Virtex-5 LX30 FPGA.

 

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Figure 5.  Direct speed comparison of new Virtex-5 LX30 FPGAs with legacy Virtex-II 1M Gate FPGA

 

Additional Resources

R Series Intelligent DAQ Frequently Asked Questions (FAQ)

FPGAs Under the Hood Whitepaper

R Series Intelligent DAQ

NI LabVIEW FPGA

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