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Overview
Frank Lloyd Wright, an influential 20th century architect, once said, “Every great architect … must be a great original interpreter of his time, his day, his age.” The same can be said for test system architects. They must interpret evolving technologies, such as multicore processors, field-programmable gate arrays (FPGAs), and high-speed data buses like PCI Express, as they design, develop, and implement the systems they have been commissioned to build. By combining these technologies with NI LabVIEW parallel programming software and NI TestStand test management software, test engineers can create high-performance test systems capable of parallel processing, parallel measurements, and even completely parallel test on the production floor. By going parallel with PC-based technologies, you can test devices up to 10 times faster than traditional instrumentation.
Parallel Processing
In traditional CPU designs, performance is limited by pragmatic challenges such as heat dissipation because of high clock rates. To ensure the PC platform continues to keep pace with increasing processing demands, chip manufacturers are developing new processors with multiple processing cores. For automated test applications to realize the performance and throughput benefits of multicore technology, software applications must target the multiple processing cores by creating multiple threads that execute on the processing cores.
Figure 1. The LabVIEW compiler creates separate execution threads for parallel sections of code,with no user configuration required.
However, writing multithreaded applications in a text-based programming language, such as ANSI C, is nontrivial for most design and test engineers and requires expertise in the semantics of creating and managing the threads and passing data among them in a thread-safe way. Using graphical programming environments such as LabVIEW, engineers can take full advantage of multicore processing power. As shown in Figure 1, two loops in LabVIEW that do not share a data dependency automatically execute in separate threads while abstracting the details of thread management away from the developer. For an example of how to take advantage of multicore processors, read the white paper titled, “Optimizing Automated Test Applications for Multicore Processors with NI LabVIEW.”
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For extreme data manipulation and signal processing, it is often necessary to dedicate processing power to these tasks alone. Multicore controllers provide one suitable avenue for this, but for the ultimate in parallel processing, it is difficult to surpass the capability of an FPGA. FPGAs, which offer unprecedented performance and reliability for automated test systems, are one of the best examples of parallel programmable computing hardware available today. The LabVIEW FPGA Module uses LabVIEW embedded technology to extend LabVIEW graphical development and target FPGAs on NI reconfigurable I/O (RIO) hardware. LabVIEW is distinctly suited for FPGA programming because it clearly represents parallelism and data flow. With the LabVIEW FPGA Module, you can create custom measurement and control hardware without low-level hardware description languages or board-level design. You can use this custom, parallel hardware for unique timing and triggering routines, ultrahigh-speed control, interfacing to digital protocols, digital signal processing (DSP), and many other applications requiring high-speed hardware reliability and tight determinism.
With FPGAs, you can implement coprocessing applications (see Figure 2). For example, by using the new fixed-point math capability of LabVIEW FPGA and the available fast Fourier transform (FFT) IP on ni.com/ipnet, you can place up to 40 parallel FFT operations onto the Virtex-5 LX50 FPGA of the NI PXI-7852 R Series module. With the dedicated bandwidth of PXI Express (up to 1 GB/s/direction) and peer-to-peer streaming on the horizon, the value of this type of capability is increasing.
Figure 2. The fixed-point math capabilities of LabVIEW FPGA enable coprocessing applications involving FFTs to exist on PXI FPGA targets for increased performance.
Parallel Measurements
Parallel measurements require that all of the subcomponents in a test system support a parallel model, not just the processor. This includes data acquisition and transfer.
Figure 3. PCI Express delivers dedicated bandwidth instead of shared data transfer, significantly increasing the amount of data that you can acquire and stream to disk.
The most common data transfer buses for modular instrumentation today – including PCI, USB, Ethernet, and GPIB – do not support a truly parallel data transfer model because the devices on the bus share bandwidth. If the cumulative rate of acquisition or generation of the I/O devices is faster than the rate at which the bus is available, data could be lost. A common solution to this problem is performing measurements sequentially and integrating large buffers of onboard memory on the I/O device so data is not lost while waiting for availability on the communications bus.
In contrast, PCI Express, the latest in high-performance data transfer buses, delivers dedicated bandwidth for each device while still providing throughput higher than any of the other commercial communications buses previously mentioned. Available in x1, x4, x8, and x16 lanes (pronounced “by 1,” “by 4,” and so on), PCI Express offers 250 MB/s of usable throughput per lane. The x1 and x4 options, which are the most common for instrument-class hardware, deliver 250 MB/s and 1 GB/s (four lanes at 250 MB/s) of dedicated throughput, respectively.
By taking advantage of PCI Express technology in the backplane, PXI Express increases the available PXI bandwidth from 132 MB/s to 6 GB/s for a more than 45 times improvement in bandwidth while still maintaining software and hardware compatibility with PXI modules. Fully integrated with the PXI platform, PXI Express gives PXI users up to 1 GB/s/direction dedicated per-slot bandwidth and the industry’s highest-performance timing and synchronization capabilities.
Figure 4. PCI Express and modular instrumentation provide a scalable model for parallel measurements.
As a PXI Express module acquires data, it is transferred from onboard memory across a dedicated PCI Express lane and streamed to a hard drive or into system memory. Once in system memory, the LabVIEW application can access the data, and, if used with a multicore processor, the parallel measurement, from signal to final measurement, is completed.
Parallel Test
With multicore processing, PCI Express, and LabVIEW, you can create parallel measurement systems capable of testing a single unit under test (UUT) at a time. The definition of parallel test, however, is multiple UUTs undergoing testing simultaneously. The alternative is to test UUTs sequentially. Although parallel test clearly reduces aggregate test times, increases test throughput, and improves instrument usage, the complexity of developing a parallel test system can be prohibitive. Developing test management software that implements the testing of multiple UUTs at once requires a low-level understanding of how the operating system works with parallel operations, such as Windows Critical Sections, and careful consideration of how to implement instrument sharing among many UUTs without creating conflicts or deadlocks.
An alternative to developing a custom parallel test system from scratch is to use off-the-shelf test management software, such as NI TestStand. This software abstracts the low-level complexity of parallel test system development using built-in features for executing parallel test sequences in multiple threads and managing both operating system and instrument resources. In addition, you can reduce test time and increase throughput by using the NI TestStand Resource Profiler to understand instrument use and parallel test system execution. The Resource Profiler analyzes test system execution and identifies instrument bottlenecks to help optimize test code and prioritize future instrument investments. The profiler displays the use of instruments and other resources in real time, as seen in Figure 5.
Figure 5. The NI TestStand Resource Profiler increases throughput by helping developers understand the execution of parallel test systems.
To illustrate the performance advantages of adopting a parallel test architecture, consider a basic W-CDMA test sequence implemented with the PXI platform versus traditional instruments. Consistent with W-CDMA test specifications, a benchmark should report both the time and accuracy of measurements such as adjacent channel power (ACP), occupied bandwidth (OBW), complementary cumulative distribution function (CCDF), and error vector magnitude (EVM). As Figure 6 illustrates, a parallel test platform based on NI TestStand, LabVIEW, and the PXI platform delivers up to a five times improvement in measurement speed. This performance can result in significant savings to the end user. For more information on this benchmark analysis, read the RF Benchmark Comparisons white paper.
Figure 6. The NI parallel test platform, based on LabVIEW, NI TestStand, and PXI, delivers up to a five times improvement in measurement speed with better accuracy than traditional instrumentation.
Completing the Parallel Test Architecture
Multicore processors, FPGAs, and PCI Express are changing the modern PC landscape and helping LabVIEW graphical programming deliver on the promise of truly parallel processing and parallel measurements based on the data flow of an engineer’s application logic. With NI TestStand, the parallel test architecture is complete. This architecture results in test systems with increased data throughput using PCI Express; increased processing power using LabVIEW, multicore processors, and FPGAs; and ultimately decreased total test time and cost per UUT using NI TestStand.
Additional Resources
Learn More about LabVIEW 8.6
- To learn more about new LabVIEW 8.6 features, visit the LabVIEW 8.6 portal at ni.com.
- To try new features, launch LabVIEW online.
Additional resources
- NI TestStand 4.1 – Accelerating Parallel Test
- Increasing Performance with Parallel Test
- Optimizing Test System Performance with Parallel Testing Technologies
- Parallel Test Architectures for Reducing the Cost to Test
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